Computer Science and Mathematics

Abstract: Agentic chip design combines large language models with electronic design automation (EDA) tools to plan, execute, and revise design operations. Its effectiveness depends on how an agent translates requirements into executable tasks, interprets diagnostic information, and coordinates changes across design stages. This survey examines these relationships across digital design, agent architectures, EDA algorithm and tool development, and evaluation, with additional coverage of analog, mixed-signal, and radio-frequency applications. We compare agentic chip-design methods through the design representations they modify, the feedback used to select revisions, and the procedures used to check correctness and implementation quality. The analysis shows that broader agent control over designs and EDA software expands optimization opportunities while increasing the need to manage dependencies and verify changes across the design flow. We also compare benchmarks and evaluation methods, focusing on functional correctness, implementation quality, and computational cost. These comparisons identify research directions in specification interpretation, failure diagnosis, repository-level integration, cross-stage optimization, and efficient tool use. By synthesizing these findings, this survey aims to guide the research community in developing and evaluating more reliable and efficient chip-design agents.

Abstract: Microgrids are increasingly built around power-electronic interfaces whose coordination depends on digital communication, and this dependence exposes them to malicious manipulation of data in transit. Because analytical and purely software studies cannot reproduce the timing, quantization, and execution effects of real controllers, credible vulnerability assessment calls for test benches in which physical hardware and emulated networks operate together. This paper describes such a bench for two parallel grid-forming inverter-based resources (IBRs) that jointly feed a shared point of common coupling (PCC). The electrical network runs on an OPAL-RT OP4610XG real-time simulator, each inverter is governed by a virtual synchronous generator (VSG) law executed on a Texas Instruments F28379D digital signal controller, and the exchange of control and measurement signals is routed through a time-synchronized EXata CPS network emulator. False data injection is applied to both a frequency setpoint and a PCC power measurement. Results obtained with a reference-driven configuration and with the hardware VSG closing the loop show that, while setpoint tampering visibly perturbs PCC voltage and power in the former, the latter keeps the operating point essentially unchanged, confirming the value of the proposed platform for real-time cyber–physical resilience studies.

Abstract: Distributed quantum computing (DQC) connects quantum processing units (QPUs) to execute programs beyond the capacity of a single processor. Understanding its scalability requires examining the interactions between hardware, communication, software, and security. This structured review synthesizes 126 studies, mainly published between 2020 and 2026 with foundational earlier work, retrieved from eight sources and selected using documented inclusion and exclusion criteria. We organize the literature into five pillars: infrastructure, protocols, applications, compilation, and security. A common scoping rule distinguishes work enabling distributed computation from broader quantum communication research. The synthesis identifies interconnect rate and fidelity, classical control latency, remote-operation overhead, and coherence constraints as coupled limits on distributed execution. Infrastructure and protocol research includes experimental demonstrations, whereas application and compiler evaluations remain predominantly simulation-based. Security requires both protected interconnects and confidential, verifiable delegated computation. Comparisons across the pillars reveal tradeoffs between local computation, communication resources, sampling overhead, and trust assumptions. The review highlights unresolved challenges in distributed fault tolerance, transduction, interoperable software, benchmarking, and integrated security. Its central conclusion is that scalable DQC requires coordinated hardware–software–network design and evaluation of complete systems rather than isolated improvements within individual layers.

Abstract: This paper documents a low-cost smart door-lock proof-of-concept with two separate control paths: local fingerprint authentication using an Arduino Uno and an R307 fingerprint sensor, and a Wi-Fi browser interface implemented on an ESP32-CAM. The biometric subsystem includes a relay, a solenoid lock, a 16×2 I²C LCD, and status LEDs. The ESP32-CAM firmware serves a browser page, a camera stream, and an HTTP action endpoint. Source-code inspection found no HTTP authentication, no JSON door-state endpoint, and no signal linking the Arduino’s biometric decision to the ESP32-CAM. The network control endpoint is therefore not protected by application-level authentication in the reviewed implementation. Because independently verifiable trial-level records were unavailable for this revision, quantitative biometric performance claims are not reported. Instead, the paper describes the architecture, firmware behavior, implementation limitations, and security improvements needed before deployment. No formal network penetration or biometric spoofing evaluation is claimed.

Abstract: FPGA acceleration of Transformer inference involves model transformation, arithmetic optimization, memory organization, and deployment. This survey critically synthesizes 266 publications (2021–2026), identifying five mechanisms underlying performance gains: computation reduction, data movement reduction, arithmetic density, hardware utilization, and computational capacity. Quantization emerges as a frequently reported optimization, while architectural rankings depend on study selection and classification. Configuration-level comparisons and break-even analyses reveal how conversion, communication, integration overhead, and model quality constrain reported benefits. Supported by a traceable evidence map, the survey identifies limitations in existing evaluations and provides practical design guidance and controlled experiments for future FPGA-based Transformer accelerators.

Abstract: Runtime adaptive FPGA execution is attractive for in-vehicle language models because the dominant bottleneck changes with context length, inference phase, and memory pressure. This work develops a ZCU102/XCZU9EG-oriented architecture with four constant-budget modes that redistribute 2,048 DSPs between attention and feed-forward processing under a stateful break-even controller. Evaluation combines checkpoint-level W8A8 screening, benchmark-derived automotive request statistics, analytical and event models, and Monte Carlo controller experiments. For SmolLM2-135M-Instruct, W8A8 screening increases WikiText-2 perplexity by 2.95%; 390,510 STRIDE-QA human turns have a median length of 14 tokens and p95 of 48. The compute model predicts an attention-heavy-mode benefit of 22.01% at 8,192 tokens. Across twenty independent 1,000-request traces per workload, the controller reduces mean modeled request latency by 1.68% for routine traffic, 16.75% for multimodal traffic, and 17.49% for long-context bursts relative to static C0. Executed W8A8 operator tests report 1.38–1.77% normalized RMSE and cosine similarity above 0.99984. These results support context-aware, transition-cost-aware resource allocation for adaptive edge language-model acceleration.

Abstract: Published rankings of GeoServer, MapServer and QGIS Server usually rest on one hand-tuned configuration per server under closed-loop load. Under a time-stamped protocol, 816 Sobol-sampled sessions per platform ran under open-loop load on exclusive nodes of two processor generations. Surrogates gave sensitivity indices and ranking probabilities. For capacity, the engine's total-order index (0.11) was below those of data complexity, image size, core count and request projection; latency was dominated by data complexity, image size and, for tail latency, the request projection. GeoServer had higher capacity than MapServer in 56% of the space, and capacity rankings reversed in 31% of workload cells on one platform and 35 to 41% for every pair on the other. At half its own capacity, GeoServer usually had the lowest median latency but the greatest relative tail inflation. The FastCGI worker count changed MapServer and QGIS Server capacity about 5.5-fold, and reprojection cost 30 to 69%. Surrogates did not transfer between processor generations. With 32 Bayesian-optimisation proposals each, GeoServer and MapServer tied within measurement resolution at a reference workload and QGIS Server reached 18% less. Rankings depended on configuration within the tested space, so benchmarks should sample configurations, use open-loop load and verify output equivalence.

Abstract: This paper presents an end-to-end system in which 4K-resolution (3840 × 2160, 12-bit, YCbCr 4:2:0) 360° panoramic color images captured by a field-mounted camera are compressed in hardware on a graphics processing unit (GPU) using the HEVC (H.265) codec, transmitted between two points (up to 1000 km apart) over a link limited to 100 Mbps using the RTP protocol within a maximum latency budget of 2 s, and then decoded in hardware on a GPU at the receiving side for live display on ten 4K monitors. The camera delivers the 360° panorama at 5 frames per second as ten 36° sectors, corresponding to a raw data rate of approximately 5 Gbps. With the hardware HEVC encoder (NVENC) of NVIDIA GPUs, the data rate is reduced to roughly one hundredth of the raw rate, at most 50 Mbps. Inter-process data sharing is implemented as a circular list in System V shared memory, coordinated with semaphores. Measurements show that the end-to-end latency remains below 1 s.

Abstract: The E80 is an open-source, 8-bit, single-cycle soft processor written in VHSIC Hardware Description Language (VHDL) from gates, multiplexers, and flip-flops, without an arithmetic package. Its 39 instructions were derived from 371 program samples in eight sources of introductory computer architecture material. They cover almost 80% of the operations recorded, averaged per source. A toolchain takes an assembly program to a simulation waveform with one keystroke. Presets cover three low-cost field-programmable gate array (FPGA) boards, one on a fully open-source flow. This extended version removes a false combinational loop from the datapath, so the design passes timing analysis on all three flows without workarounds. A serial light-emitting diode (LED) matrix mirrors the simulation signals on the board. Execution can be slowed or stepped one instruction at a time. A self-checking program decides the conformance of every instruction from the final program counter alone. The largest program in the surveyed material, a recursive maze search written for a 16-bit machine, was ported without abridgement into 208 of the 255 memory words. The effect on learning remains unmeasured.

Abstract: With the development of smart agriculture, agricultural big data typically exhibit characteristics such as long-term accumulation and multi-source heterogeneity, which place higher demands on secure storage and sustained decryptability in long-running environments. To address this issue, this paper proposes CD-KLM, a secure storage architecture for Hadoop-based agricultural big data platforms. Specifically, we adopt a client-driven, server-lightweight-collaborative design, in which the reading and decryption capabilities of historical files are independently controlled by the client, while the server only issues collaborative salt values to authenticated clients during new-file creation. On this basis, a dynamic working-key derivation mechanism is designed based on HKDF and file-related contextual information, so that working keys no longer need to be persistently stored over the long term, thereby reducing the risk of malicious data decryption caused by prolonged exposure of critical key material. Meanwhile, threshold-based key recovery is unified at the root-key level, enabling the system to restore its overall decryption capability even when critical keys are damaged or lost. Experimental results in a Hadoop distributed environment show that, while ensuring key recoverability and continuous decryptability, the proposed architecture imposes only a low impact on system throughput, making it suitable for long-running secure storage scenarios for agricultural big data.

Abstract: Preserved-context execution retains microarchitectural state across scheduler-induced context changes, but this state is not automatically useful for deciding which runnable context should execute next. This work investigates whether pre-activation pipeline state can provide a secondary ranking signal among contexts already equivalent under the primary scheduler. A short-horizon recovery metric, R(H), quantifies instructions retired immediately after activation. Preserved-state traces are used to evaluate recovery rankability, examine compact offline representations, reconstruct the deployed 16-bit C16 descriptor, and compare four progressively informed policies. The deployed C16 descriptor achieves 84.63% pooled and 86.81% unweighted macro pairwise ranking accuracy, compared with 93.36% and 93.34%, respectively, for the full-state reference. The final S3 policy combines C16 with a guarded bounded-residency rule that preserves primary scheduler authority. Across 40 matched base configurations each evaluated under S0–S3, S3 improves mean configuration-level R(4) by 0.2574 retired instructions over the deterministic S0 baseline and produces a positive S3–S0 difference in 32 of the 40 matched comparisons. The 95% BCa bootstrap confidence interval is [0.1719, 0.3782], and the exact Wilcoxon signed-rank test confirms a positive paired shift (W=69, p=4.77×10^-7). These results show that preserved microarchitectural state can support recovery-aware scheduling when state representation and policy design are considered jointly.

Abstract: Voxel-based video games offer an interactive platform for simulating complex digital logic architectures. This paper presents the design and functional evaluation of a redstone arithmetic calculator capable of performing addition and subtraction on two three-digit numbers within Minecraft Java Edition Version 1.21.1. Hosted on a Spigot/Paper server fixed at 20 game ticks per second, the system establishes a deterministic operational clock to eliminate signal disconnection and timing race conditions across circuit arrays. Decimal inputs from a ten-key button panel are encoded into 4-bit Binary-Coded Decimal (BCD) representations via a diode matrix and latched using D Flip-Flop registers. A weighted combinational translator aggregates positional values into a unified binary format optimized for computation. The central Arithmetic Logic Unit executes bitwise addition and Two’s Complement subtraction governed by an RS Flip-Flop control line, with data routed across a synchronized parallel bus featuring passive delay calibration. The binary output is converted back into decimal format through a Double Dabble shift-add-three architecture to drive a seven-segment redstone Lamp display. Experimental results confirm deterministic signal execution and accurate visual output across all valid operations, demonstrating that spatial gaming environments serve as viable platforms for visualizing physical hardware design and computer engineering principles.

Abstract: Real-time quantum error correction requires a classical decoder to consume syndrome measurements at the rate the quantum hardware produces them, roughly one round per microsecond on supercon-ducting devices. The standard stability requirement is a utilization condition: the mean decode time per round must be less than the round period, ρ < 1. We show that this condition is inadequate for windowed decoders whose per-window cost grows superlinearly in the number of detection events, which is the empirical shape of matching-based decoders under burst-like syndrome content. For this class, stability is not a threshold but a basin. The deterministic backlog dynamics have a stable operating point and an unstable boundary B^∗. Noise erodes that boundary downward, and sufficiently superlinear decoders escape spontaneously. In discrete-event simulations paired under common random numbers, a decoder with cost exponent γ = 1.5 and mean utilization ρ₀ = 0.6 (forty percent nominal headroom) fails without provocation, with a mean time to failure of 1,344 ± 289 rounds, about 1.3 ms of wall clock at a 1 μs cycle. These Poisson times are upper bounds: modulating the arrival rate at fixed mean load shortens them monotonically with the measured dispersion index of the arrivals, fourfold by D ≈ 3, and a dispersion excess of twelve percent already uncensors the ρ₀ = 0.5 ensemble. We measure the cost exponent of a production decoder (PyMatching 2, sparse blossom) and find it anisotropic: near-linear (γ ≈ 1.1–1.2) when a window grows in length at fixed syndrome density, but approximately quadratic (γ ≈ 2) when the same window grows denser. Bursts travel along the dangerous axis, where the basin is 2–4 rounds deep for ρ₀ between 0.5 and 0.8. Spatially clustered event content, the syndrome footprint of leakage and cosmic-ray bursts, is worse still: at matched event count, clustered windows cost 7.6× length-grown ones and 4.8× uniformly densified ones, so the quadratic density exponent is a conservative proxy for burst content. The anisotropy is a property of the matching class rather than of one implementation, since a second exact-MWPM decoder reproduces the density exponent, while a BP+OSD decoder is nearly event-independent: no basin, but orders of magnitude more cost per window. The basin is the price of event-adaptive decoding. Greedy catch-up (“decode everything queued”) is precisely the divergent policy. A bounded decoding window restores stability, and the measured stability edge lands on a closed-form line. The rule survives finite memory: under greedy service a queue cap acts as an implicit window, and a cap on the unstable side of the same line pins at the cap and sheds rounds indefinitely, so adding buffer memory makes the greedy policy strictly worse. The simulation model is cross-validated against Stim at the level of individual fault mechanisms.

Abstract: Kernel-bypass storage designs built on Linux io_uring’s IORING_SETUP_SQPOLL mode are motivated by a simple argument: a dedicated kernel polling thread removes the per-operation syscall that blocking and non-polling asynchronous I/O interfaces pay, so on modern NVMe hardware, where flash latency is no longer the bottleneck, SQPOLL should win on throughput. We built ringio, a header-only C++20 storage engine around this argument, and tested it against libaio and plain io_uring (no SQPOLL) on a virtualized cloud NVMe device across two machine sizes (4 and 16 vCPUs) and a swept queue-depth and thread-count matrix, alternating 4KB random reads and writes. The argument does not hold once the device itself saturates: at matched thread count and queue depth, SQPOLL does not beat the syscall-based baselines on raw IOPS at either machine size once concurrency is high enough to reach the device’s roughly 200K-IOPS ceiling, ruling out core oversubscription as the explanation for that plateau. Below the plateau, at a single thread, the gap is starker still: libaio reaches more than double SQPOLL’s throughput on the same hardware, a gap that widens rather than narrows on the wider box. SQPOLL’s tail latency also degrades under more available cores rather than improving. What SQPOLL does deliver is a large reduction in kernel entries per completed operation, roughly an order of magnitude fewer than plain io_uring at high queue depth, at the cost of that added tail latency. Reading this alongside two recent studies that do report SQPOLL wins in CPU-bound settings, our results are consistent with a resolution neither we nor they test directly: SQPOLL’s advantage is conditional on the CPU or syscall path being the bottleneck, and it disappears once a saturated device becomes the limit first. A sweep of sq_thread_idle across four orders of magnitude leaves throughput, tail latency, and kernel entries per operation unchanged, ruling that parameter out as the explanation: the poller never reaches its idle timeout under this workload. We report the full methodology, including a page-cache measurement defect that invalidated an earlier round of results, and discuss what this suite’s data does and does not establish about the underlying cause.

Abstract: Agriculture underpins rural livelihoods in Cambodia, where roughly 1.85 million holdings across 3.2 million hectares are overwhelmingly smallholder, averaging 1.7 hectares each. On plots of this size, field scouting is still performed on foot: the method is slow, physically demanding, and epistemically limited, as the observer sees the crop from within the canopy and localised pest, weed, or irrigation problems are noticed only once they grow conspicuous from ground level. A second gap concerns memory, as the location of an outbreak is retained informally and is generally unrecoverable on a return visit. Commercial agricultural unmanned aerial vehicles (UAVs) address both limitations but are priced for enterprise-scale operations and cannot be justified across a 1.7-hectare holding. This paper presents AgriMap, a low-cost aerial field-monitoring platform pairing an open-hardware F450 quadcopter with an automated routine that triggers the camera every five seconds, stamping each frame with latitude, longitude, altitude, and battery state. Frames are stored in a Laravel and MySQL backend and rendered as interactive Leaflet markers over a field basemap, producing a persistent, searchable inspection record. Mission logic and operator workflow were validated in a Unity simulation prior to deployment. The system was assembled for USD 256.70, and all hardware specifications and dashboard source code are released openly.

Abstract: The feasibility of executing learned line-segment detectors on microcontroller-class hardware has remained an open question, despite their proven accuracy on graphics processors and the emergence of compact variants such as MiLSD that is ostensibly sized for embedded memory budgets. This work proposes FOLD (Framework for On-Device Line-Segment Detection), an end-to-end deployment methodology for fully-convolutional line detectors. The framework bridges the gap between network representation and on-chip execution across the STM32 family. It is validated on actual hardware at four operating points: a 25k-parameter F-Clip baseline on an STM32F746, MiLSD across four STM32H7 boards, and two NPU-native detectors (NPLSD-M and NPLSD-H) on an STM32N6.On the STM32H7B3, int8 MiLSD runs at 10.6 s per inference with an 847 KB on-chip arena. The same model cannot be deployed on the faster STM32H743 due to fragmented SRAM, confirming that memory layout, not capacity, governs deployability. On the NPU class, a key finding is that int8 quantization, not a convolutional graph alone, engages the accelerator. In int8, NPLSD-H runs in 33.7 ms at sAP¹⁰=35.9 entirely in on-chip SRAM, a 698× speedup over MiLSD. NPLSD-M reaches sAP¹⁰=41.1 in 121.7 ms. The framework yields a measured tier map from CPU-only boards to a real-time NPU operating point. An edge-GPU reference (LINEA-N on Jetson Xavier NX: sAP¹⁰=63.9 at 101 ms, 1.34 J) bounds the map from above. All on-chip outputs match the reference models to cosine 1.000.

Abstract: For six decades Moore's Law has guided the semiconductor industry, but dimensional scaling is now meeting hard physical and economic limits. Here we argue that the post-Moore era needs a figure of merit anchored to physical invariants rather than to calendar time. We introduce the spatiotemporal efficiency \(\Lambda = N f /(P V)\), combining transistor count \(N\), clock frequency \(f\), power \(P\) and heat-dissipating volume \(V\). Once the total switching power is accounted for, both \(N\) and \(f\) cancel and \(\Lambda\) reduces to the device energy efficiency divided by volume. Because the thermal resistance of a three-dimensional stack grows linearly with height, \(\Lambda\) falls as \(1/V\)—a relation we call the Volume-Inverse Law. Bounded by Planck's constant and the Landauer limit, it recasts the central competition of the post-Moore era as computation per unit volume, and predicts a finite optimal stacking height and a decisive shift toward energy-efficient, architecture-led design.

Abstract: Configurable intelligent design is formalized here as the selection of a consistent configuration from interdependent alternatives under strict constraints of budget, quality, risk, and compatibility. Locally correct predictions for individual components do not guarantee a globally feasible solution. The objective of this study is to quantify the differences among direct neural network inference, the exact deterministic HIM-D solver, and a procedural hybrid architecture in which a neural network proposes a candidate, an independent verifier checks all constraints, and control is transferred to an exact search whenever at least one condition is violated. For the experiment, a reproducible synthetic corpus of 24,000 configuration problems spanning educational, engineering, and commercial scenarios was generated. Feasibility of solutions, joint feasibility and optimality, robustness to distribution shift, repeatability, and computational latency were assessed. Pure neural network models achieved feasible solutions in only 17.40% and 19.12% of cases and showed pronounced degradation under out-of-distribution (OOD) conditions. The procedural hybrid maintained 100% feasibility and achieved 83.08% on the composite feasibility-and-optimality metric. These results confirm the effectiveness of architecturally separating probabilistic prediction from independent formal verification when solving configuration problems with tight constraints.

Abstract: The growing use of RISC-V processors in real-time embedded systems has increased the need for evaluation methods that can characterize timing behavior under scheduler-driven workloads. While existing simulation environments provide extensive support for architectural exploration and functional validation, they are not primarily designed for controlled timing-scalability studies across large configuration spaces. This paper presents nSim-RV, a configurable RISC-V simulation and orchestration framework developed for reproducible evaluation of timing behavior under increasing workload density. The framework combines automated campaign generation, structured dataset aggregation, validation procedures, and timing-oriented analysis within a unified workflow. The evaluation includes CoreMark, Dhrystone, and synthetic RT-Control workloads, task counts ranging from 2 to 32 concurrent tasks, observation windows from 50k to 1M cycles, cache-disabled and cache-enabled configurations, and both 4-stage and 5-stage pipeline organizations. A comparative analysis is performed between a Standard shared-pipeline execution model and an nMPRA-inspired preserved-context execution mode across 864 validated pipeline-specific configurations. Under cache-disabled conditions, response-time variability, execution jitter, and deadline miss ratio all increase monotonically with task count for both execution modes, with the most pronounced growth observed beyond N = 8 concurrent tasks. Preserved-context execution reduces switching-induced disturbance and delays the onset of saturation-phase behavior across the majority of evaluated trajectories, with the clearest benefit appearing in Dhrystone and RT-Control workloads at intermediate to high task counts.

Abstract: This paper presents TALOS, a beyond-state-of-the-art unified-reusable 6G CryptoProcessor architecture for high-assurance symmetric security services under a 256-bit private-key operating baseline. The work is driven by a fundamental hardware-design challenge: future 6G systems will require simultaneous support for heterogeneous strong symmetric primitives; yet conventional per-cipher hardware replication is area-intensive, power-inefficient, and structurally unflexible. TALOS addresses this problem through a processor oriented architecture that combines a Hierarchical Common Data Path (HCDP) with a three-tier cryptographic encapsulation model spanning AES-256, Snow 5G/SNOW-V class, and ZUC-256. The proposed methodology separates reusable structures by exact operator class: Tier-1 captures native nonlinear substitutions, Tier-2 captures bounded arithmetic nonlinearities through micro-S-box compilation, and Tier-3 captures shared permutations, XOR, affine, diffusion, and state-transport fabrics. This decomposition enables for exact operator-level unification without forcing structurally dissimilar cipher families into an artificial common form. As a result, TALOS preserves cipher correctness while exposing the strongest realistic sharing opportunities across the substitution, arithmetic, and linear transport layers. The architecture further supports (CIA) confidentiality processing together with integrity- and authentication-supporting service integration through a common control and resource framework. In contrast to monolithic universal-box concepts or loosely aggregated multi-core designs, TALOS establishes a disciplined and scalable hardware taxonomy for crypto-agile 6G symmetric-core realization. The proposed framework, therefore, advances the state of the art by unifying rigorous methodological exactness, architectural reuse, and implementation-oriented practicality within a single CryptoProcessor design paradigm.