Computer Science and Mathematics

Abstract: The feasibility of executing learned line-segment detectors on microcontroller-class hardware has remained an open question, despite their proven accuracy on graphics processors and the emergence of compact variants such as MiLSD that is ostensibly sized for embedded memory budgets. This work proposes FOLD (Framework for On-Device Line-Segment Detection), an end-to-end deployment methodology for fully-convolutional line detectors. The framework bridges the gap between network representation and on-chip execution across the STM32 family. It is validated on actual hardware at four operating points: a 25k-parameter F-Clip baseline on an STM32F746, MiLSD across four STM32H7 boards, and two NPU-native detectors (NPLSD-M and NPLSD-H) on an STM32N6.On the STM32H7B3, int8 MiLSD runs at 10.6 s per inference with an 847 KB on-chip arena. The same model cannot be deployed on the faster STM32H743 due to fragmented SRAM, confirming that memory layout, not capacity, governs deployability. On the NPU class, a key finding is that int8 quantization, not a convolutional graph alone, engages the accelerator. In int8, NPLSD-H runs in 33.7 ms at sAP¹⁰=35.9 entirely in on-chip SRAM, a 698× speedup over MiLSD. NPLSD-M reaches sAP¹⁰=41.1 in 121.7 ms. The framework yields a measured tier map from CPU-only boards to a real-time NPU operating point. An edge-GPU reference (LINEA-N on Jetson Xavier NX: sAP¹⁰=63.9 at 101 ms, 1.34 J) bounds the map from above. All on-chip outputs match the reference models to cosine 1.000.

Abstract: For six decades Moore's Law has guided the semiconductor industry, but dimensional scaling is now meeting hard physical and economic limits. Here we argue that the post-Moore era needs a figure of merit anchored to physical invariants rather than to calendar time. We introduce the spatiotemporal efficiency \(\Lambda = N f /(P V)\), combining transistor count \(N\), clock frequency \(f\), power \(P\) and heat-dissipating volume \(V\). Once the total switching power is accounted for, both \(N\) and \(f\) cancel and \(\Lambda\) reduces to the device energy efficiency divided by volume. Because the thermal resistance of a three-dimensional stack grows linearly with height, \(\Lambda\) falls as \(1/V\)—a relation we call the Volume-Inverse Law. Bounded by Planck's constant and the Landauer limit, it recasts the central competition of the post-Moore era as computation per unit volume, and predicts a finite optimal stacking height and a decisive shift toward energy-efficient, architecture-led design.

Abstract: Real-time quantum error correction requires a classical decoder to consume syndrome measurements at the rate the quantum hardware produces them, roughly one round per microsecond on supercon-ducting devices. The standard stability requirement is a utilization condition: the mean decode time per round must be less than the round period, ρ < 1. We show that this condition is inadequate for windowed decoders whose per-window cost grows superlinearly in the number of detection events, which is the empirical shape of matching-based decoders under burst-like syndrome content. For this class, stability is not a threshold but a basin. The deterministic backlog dynamics have a stable operating point and an unstable boundary B^∗. Noise erodes that boundary downward, and sufficiently superlinear decoders escape spontaneously. In discrete-event simulations paired under common random numbers, a decoder with cost exponent γ = 1.5 and mean utilization ρ₀ = 0.6 (forty percent nominal headroom) fails without provocation, with a mean time to failure of 1,344 ± 289 rounds, about 1.3 ms of wall clock at a 1 μs cycle. These Poisson times are upper bounds: modulating the arrival rate at fixed mean load shortens them monotonically with the measured dispersion index of the arrivals, fourfold by D ≈ 3, and a dispersion excess of twelve percent already uncensors the ρ₀ = 0.5 ensemble. We measure the cost exponent of a production decoder (PyMatching 2, sparse blossom) and find it anisotropic: near-linear (γ ≈ 1.1–1.2) when a window grows in length at fixed syndrome density, but approximately quadratic (γ ≈ 2) when the same window grows denser. Bursts travel along the dangerous axis, where the basin is 2–4 rounds deep for ρ₀ between 0.5 and 0.8. Spatially clustered event content, the syndrome footprint of leakage and cosmic-ray bursts, is worse still: at matched event count, clustered windows cost 7.6× length-grown ones and 4.8× uniformly densified ones, so the quadratic density exponent is a conservative proxy for burst content. The anisotropy is a property of the matching class rather than of one implementation, since a second exact-MWPM decoder reproduces the density exponent, while a BP+OSD decoder is nearly event-independent: no basin, but orders of magnitude more cost per window. The basin is the price of event-adaptive decoding. Greedy catch-up (“decode everything queued”) is precisely the divergent policy. A bounded decoding window restores stability, and the measured stability edge lands on a closed-form line. The rule survives finite memory: under greedy service a queue cap acts as an implicit window, and a cap on the unstable side of the same line pins at the cap and sheds rounds indefinitely, so adding buffer memory makes the greedy policy strictly worse. The simulation model is cross-validated against Stim at the level of individual fault mechanisms.

Abstract: Configurable intelligent design is formalized here as the selection of a consistent configuration from interdependent alternatives under strict constraints of budget, quality, risk, and compatibility. Locally correct predictions for individual components do not guarantee a globally feasible solution. The objective of this study is to quantify the differences among direct neural network inference, the exact deterministic HIM-D solver, and a procedural hybrid architecture in which a neural network proposes a candidate, an independent verifier checks all constraints, and control is transferred to an exact search whenever at least one condition is violated. For the experiment, a reproducible synthetic corpus of 24,000 configuration problems spanning educational, engineering, and commercial scenarios was generated. Feasibility of solutions, joint feasibility and optimality, robustness to distribution shift, repeatability, and computational latency were assessed. Pure neural network models achieved feasible solutions in only 17.40% and 19.12% of cases and showed pronounced degradation under out-of-distribution (OOD) conditions. The procedural hybrid maintained 100% feasibility and achieved 83.08% on the composite feasibility-and-optimality metric. These results confirm the effectiveness of architecturally separating probabilistic prediction from independent formal verification when solving configuration problems with tight constraints.

Abstract: The growing use of RISC-V processors in real-time embedded systems has increased the need for evaluation methods that can characterize timing behavior under scheduler-driven workloads. While existing simulation environments provide extensive support for architectural exploration and functional validation, they are not primarily designed for controlled timing-scalability studies across large configuration spaces. This paper presents nSim-RV, a configurable RISC-V simulation and orchestration framework developed for reproducible evaluation of timing behavior under increasing workload density. The framework combines automated campaign generation, structured dataset aggregation, validation procedures, and timing-oriented analysis within a unified workflow. The evaluation includes CoreMark, Dhrystone, and synthetic RT-Control workloads, task counts ranging from 2 to 32 concurrent tasks, observation windows from 50k to 1M cycles, cache-disabled and cache-enabled configurations, and both 4-stage and 5-stage pipeline organizations. A comparative analysis is performed between a Standard shared-pipeline execution model and an nMPRA-inspired preserved-context execution mode across 864 validated pipeline-specific configurations. Under cache-disabled conditions, response-time variability, execution jitter, and deadline miss ratio all increase monotonically with task count for both execution modes, with the most pronounced growth observed beyond N = 8 concurrent tasks. Preserved-context execution reduces switching-induced disturbance and delays the onset of saturation-phase behavior across the majority of evaluated trajectories, with the clearest benefit appearing in Dhrystone and RT-Control workloads at intermediate to high task counts.

Abstract: This paper presents TALOS, a beyond-state-of-the-art unified-reusable 6G CryptoProcessor architecture for high-assurance symmetric security services under a 256-bit private-key operating baseline. The work is driven by a fundamental hardware-design challenge: future 6G systems will require simultaneous support for heterogeneous strong symmetric primitives; yet conventional per-cipher hardware replication is area-intensive, power-inefficient, and structurally unflexible. TALOS addresses this problem through a processor oriented architecture that combines a Hierarchical Common Data Path (HCDP) with a three-tier cryptographic encapsulation model spanning AES-256, Snow 5G/SNOW-V class, and ZUC-256. The proposed methodology separates reusable structures by exact operator class: Tier-1 captures native nonlinear substitutions, Tier-2 captures bounded arithmetic nonlinearities through micro-S-box compilation, and Tier-3 captures shared permutations, XOR, affine, diffusion, and state-transport fabrics. This decomposition enables for exact operator-level unification without forcing structurally dissimilar cipher families into an artificial common form. As a result, TALOS preserves cipher correctness while exposing the strongest realistic sharing opportunities across the substitution, arithmetic, and linear transport layers. The architecture further supports (CIA) confidentiality processing together with integrity- and authentication-supporting service integration through a common control and resource framework. In contrast to monolithic universal-box concepts or loosely aggregated multi-core designs, TALOS establishes a disciplined and scalable hardware taxonomy for crypto-agile 6G symmetric-core realization. The proposed framework, therefore, advances the state of the art by unifying rigorous methodological exactness, architectural reuse, and implementation-oriented practicality within a single CryptoProcessor design paradigm.

Abstract: With the standardization of the Module-Lattice-Based Key Encapsulation Mechanism (ML-KEM) in NIST FIPS 203 (2024), efficient hardware support for polynomial ring operations has become critical for practical post-quantum cryptography deployment. The dominant computational workload of ML-KEM arises from matrix–vector multi-plications over polynomial rings, which involve repeated Number Theoretic Transform (NTT), pointwise multiplication, and modular addition operations. This work proposes an ML-KEM polynomial ring accelerator leveraging Open Intellectual Property (Open IP) and integrates it into an open hardware Chipyard RISC-V System-on-Chip (SoC) via a Memory-Mapped I/O (MMIO) interface. The design incorporates an NTT-based datapath with multiplier and adder arrays, and employs a scratchpad memory to enable intermediate data reuse and reduce memory access overhead. The proposed architecture is implemented on a Kintex-7 Field Programmable Gate Array (FPGA) platform and evaluated at both kernel and system levels. Experimental results show that the accelerator reduces matrix–vector multiplication latency to 7,372 cycles, achieving up to 40× speedup over a software baseline. At the SoC level, the complete ML-KEM implementation achieves performance improvements of 1.6× to 2.1× across different parameter sets. These results demonstrate that integrating Open IP within an open hardware SoC provides an effective and reproducible approach for accelerating ML-KEM.

Abstract: This paper presents the Spike Processing Unit (SPU), a digital spiking neuron model based on a discrete-time second-order Infinite Impulse Response (IIR) filter. By constraining filter coefficients to powers of two, the SPU implements all internal operations via shift-and-add arithmetic on 6-bit signed integers, eliminating general-purpose multipliers. Unlike traditional models, computation in the SPU is fundamentally temporal; spike timing emerges from the interaction between input events and internal IIR dynamics rather than signal intensity accumulation. The model’s efficacy is evaluated through a temporal pattern discrimination task. Using Particle Swarm Optimization (PSO) within a hardware-constrained parameter space, a single SPU is optimized to emit pattern-specific spikes while remaining silent under stochastic noise. Results from cycle-accurate Python simulations and synthesizable VHDL implementations indicate that the learned temporal dynamics are preserved under hardware-constrained digital execution, supporting the feasibility of the proposed approach. This work demonstrates that discrete-time IIR-based neurons enable reliable temporal spike processing under strict quantization and arithmetic constraints.

Abstract: This article presents AgroNova, an intelligent and autonomous Internet of Things (IoT) platform developed for real-time monitoring and control of the microclimate in greenhouses. The system combines distributed wireless sensor nodes, actuator mod-ules, a local gateway equipped with a rule-based control agent, and a cloud infra-structure for data visualization and decision support. The platform’s hybrid architec-ture enables autonomous operation in the event of internet failures and at the same time allows the integration of a large language model (LLM) for context-based deci-sions. AgroNova was implemented in a tomato greenhouse and validated over a period of seven months, during which over 400,000 environmental data points were recorded. The system effectively kept temperature and humidity within optimal agronomic ranges and reduced deviation time compared to manual control. In experimental tests, the LLM component generated relevant recommendations under complex conditions, such as bad weather. The results show that AgroNova is a reliable and scalable solution for greenhouse microclimate management. The combination of local autonomy and cloud intelligence of the platform offers promising applications in precision agriculture. Future work in-cludes extending the scope of LLM-assisted reasoning and adapting the platform to additional crops and greenhouse environments.

Abstract: The rise of Large Language Models (LLMs) has redefined the landscape of artificial intelligence, with the Transformer architecture serving as the foundational backbone for these breakthroughs. Despite their algorithmic dominance, Transformers impose extreme computational and memory demands that render general-purpose processing elements (PEs), such as standard CPUs and GPUs, increasingly inefficient in terms of power density and throughput. As the industry moves toward domain-specific accelerators, there is a critical need for specialized digital design strategies that address the "Memory Wall" and the quadratic complexity of attention mechanisms. This paper presents a comprehensive tutorial on the most efficient hardware architectures for implementing Transformer components in digital logic. We provide a bottom-up analysis of the hardware realization of Multi-Head Attention (MHA), Feed-Forward Networks (FFN), and non-linear normalization units like Softmax and LayerNorm. Specifically, we explore state-of-the-art implementation techniques, including Systolic Arrays for linear projections, CORDIC and LUT-based approximations for non-linearities, and the emerging SwiGLU gated architectures. Furthermore, we discuss the latest trends in hardware-software co-design, such as the use of FlashAttention-4 and Tensor Memory (TMEM) pathways to minimize on-chip data movement. This tutorial serves as a guide for computer engineers and researchers to bridge the gap between high-level Transformer mathematics and low-level RTL-optimized hardware.

Abstract: While alignment tuning aims to constrain undesirable outputs, its interaction with prompt sensitivity in video diffusion models has not been systematically quantified. This study examines how minor semantic perturbations in prompts affect bias emergence in aligned versus unaligned video diffusion systems. We generate 26,700 video samples using paired prompts with controlled lexical and contextual variations. Bias amplification is measured using demographic skew ratios, attribute co-occurrence statistics, and visual saliency attribution. Results indicate that aligned models exhibit 34.1% higher sensitivity to prompt perturbations in socially sensitive contexts, leading to amplified bias variance across outputs. These findings suggest that alignment tuning may unintentionally increase model fragility to prompt-level noise, posing challenges for reliable bias mitigation.

Abstract: Video diffusion models integrate visual, temporal, and textual signals, creating potential pathways for cross-modal bias transfer. This paper studies how alignment tuning affects the transmission of social bias between text and visual modalities in video generation. We evaluate 14,200 text-to-video samples using a cross-modal attribution framework that decomposes bias contributions across input modalities. Quantitative analysis reveals that alignment tuning reduces text-conditioned bias by 24.8%, yet increases visually induced bias carryover by 31.5%, particularly in identity-related scenarios. The results demonstrate that alignment tuning redistributes bias across modalities rather than eliminating it, highlighting the need for modality-aware alignment strategies.

Abstract: Achieving low latency and high reliability simultaneously remains a fundamental trade-off in parallel register array frameworks. This paper introduces a system-level reliability–latency co-optimization model for parallel register array communication under fault-prone environments. The proposed approach formulates path selection and redundancy allocation as a constrained optimization problem, where latency minimization is balanced against probabilistic reliability guarantees. A heuristic solver is developed to efficiently compute near-optimal configurations for large-scale register arrays. Extensive fault injection experiments were conducted on register arrays with up to 8192 registers, considering both transient and permanent faults. Compared with fixed-configuration parallel frameworks, the proposed model achieves an average latency reduction of 21.5% while maintaining reliability above 97% across all tested fault scenarios. Sensitivity analysis further shows that the model adapts effectively to varying fault distributions, with latency degradation limited to less than 8% under worst-case fault clustering. These findings provide a quantitative foundation for reliability-aware design of parallel register array systems.

Abstract: This paper reviews digital floating-point arithmetic algorithms that employ Taylor series expansion combined with mantissa region division techniques, drawing upon the results of our research. In many scientific computing applications, compact and low-power hardware implementations are essential. To address these requirements, this review presents algorithms specifically designed to operate under such constraints. The focus is placed on efficient floating-point operations—including division, inverse square root, square root, exponentiation, and logarithmic functions—all realized through Taylor series expansions. Furthermore, the paper examines the trade-offs involved, such as the number of additions, subtractions, and multiplications, as well as the hardware cost associated with Look-Up Table (LUT) size. These factors are analyzed to identify the most suitable algorithms for engineering applications and to facilitate their practical implementation.

Abstract: This paper presents a complete, constructive derivation of the Steane [[7,1,3]] quantum error-correcting code using a unified framework that bridges GF(4) algebra, binary symplectic representation, and stabilizer formalism. We demonstrate how classical coding theory, finite-field arithmetic, and symplectic geometry naturally converge to form a comprehensive foundation for quantum error correction. Starting from the classical Hamming [7,4,3] code, we provide explicit constructions showing: (1) how GF(4) encodes the Pauli group modulo phases, (2) how the symplectic inner product on F²ⁿ₂ captures commutativity, (3) how syndrome extraction reduces to binary matrix multiplication, and (4) how transversal Clifford gates emerge from symplectic transformations. The step-by-step derivation encompasses stabilizer construction, centralizer analysis, logical operator identification, code distance verification, and fault-tolerant syndrome measurement via flagged circuits. All results are derived using elementary finite-field and binary linear algebra, ensuring the exposition is self-contained and accessible. We further illustrate how this algebraic framework extends naturally to modern quantum LDPC codes. This work serves as both a pedagogical tutorial for students entering quantum error correction and a unified reference for researchers implementing stabilizer codes in practice

Abstract: We introduce ESDM–SMTJ, an Entropic Semantic Dynamics Model implemented on clas- sical probabilistic hardware based on superparamagnetic tunnel junctions (SMTJs). The model represents the internal state of a symbolic or cognitive system as a trajectory Σ(τ ) in a layered state space, with τ ∈ [0, 1] interpreted as an internal computation time from initial query to final answer. Each expression e (for example 2 + 2 =?) induces a program-specific dynamics U τ e that iteratively updates Σ(τ ). Ambiguous operators such as “+” are treated as multi-modal : every occurrence admits a finite family of semantic modes i, and an entropic gate scores each mode by the predicted reduction ∆H(k) i of the output entropy if that mode is selected at position k. These scores are mapped to effective energy levels E(k) i = E0 − κ∆H(k) i in a local SMTJ p-bit block, whose Boltzmann statistics implement a softmax distribution over modes at the hardware level. The resulting dynamics exhibits rumination (high-entropy plateaus), insight-like transi- tions (sharp entropy drops) and stabilization in low-entropy attractors, together with a natural notion of semantic commit at an internal time τc < 1 and a blind reveal of the output token via SMTJ readout at τf ≈ 1. We illustrate how simple arithmetical judgements—including rare anomalies such as 2 + 2 → 5 under mis-tuned parameters—can be expressed in this frame- work, and we outline a quantum extension in which semantic modes become basis states of a Hamiltonian with complex amplitudes instead of classical probabilities.

Abstract: With the rapid growth of secure communication and data integrity needs in embedded and networked systems, there is a growing demand for cryptographic solutions that are not only secure but also energy- and area-efficient. While software-based SHA-3 implementations offer flexibility, they often fall short in meeting the tight performance and power budgets of modern resource-constrained environments. This paper presents a hardware-accelerated SHA-3 implementation optimised for the Xilinx Artix-7 FPGA. The proposed architecture features a fully pipelined Keccak-f[1600] core and leverages techniques such as partial loop unrolling, clock gating, and pipeline balancing to improve efficiency. Designed in VHDL and synthesised using Vivado 2024.2.2, the accelerator achieves a throughput of 1.35 Gbps at 210 MHz with a total power consumption of just 0.94 W—resulting in an energy efficiency of 1.44 Gbps/W. The design is validated against NIST SHA-3 test vectors and demonstrates a strong balance between speed, low power, and hardware utilisation. These characteristics make it well-suited for deployment in secure embedded applications, such as IoT devices, edge nodes, and real-time authentication systems.

Abstract: Side-channel attacks leveraging microarchitectural components such as caches and translation lookaside buffers (TLBs) pose increasing risks to cryptographic and machine-learning workloads. This paper presents a comparative study of performance and side-channel leakage under two page-size configurations—standard 4KB pages and 2MB huge pages—using paired attacker–victim experiments instrumented with both Performance Monitoring Unit (PMU) counters and precise per-access timing using rdtscp(). The victim executes repeated, key-dependent memory accesses across eight cryptographic modes (AES, ChaCha20, RSA, and ECC variants) while the attacker records eight PMU features per access (cpu-cycles, instructions, cache-references, cache-misses, etc.) and precise rdtscp() timing. The resulting traces are analyzed using a multilayer perceptron classifier to quantify key-dependent leakage. Results show that the 2MB huge-page configuration achieves a comparable key-classification accuracy (mean 0.79 vs. 0.77 for 4KB) while reducing average CPU cycles by approximately 11%. Page-index identification remains near random chance (3.6--3.7% for PMU side-channels and 1.5% for timing side-channel), indicating no increase in measurable leakage at the page level. These findings suggest that huge-page mappings can improve runtime efficiency without amplifying observable side-channel vulnerabilities, offering a practical configuration for balancing performance and security in user-space cryptographic workloads.

Abstract: The exponential growth in global data generation has elevated the role of data centers in modern society. However, their immense energy requirements raise significant environ-mental concerns. This paper aims to demonstrate that current innovations in data center cooling systems, server placement architectures, and virtualization techniques are not on-ly technologically advanced but also critical drivers of energy sustainability. Through an in-depth review of current research, development of key technological pathways, and de-tailed discussion supported by 40 scholarly references, we establish that sustaina-ble data centers are not a futuristic ideal but a present necessity. The analysis is grounded in rigorous scientific methodologies, including thermodynamic modeling, computational fluid dynamics (CFD), and workload orchestration frameworks. By integrating energy-aware designs with cutting-edge software deployment models, data centers are being transformed from energy-intensive infrastructures into hubs of sustainable computational power. This transformation is supported not only by theoretical principles but also by a growing body of empirical data that demonstrates marked improvements in energy usage efficiency (PUE), carbon footprint (CUE), and overall sustainability metrics.

Abstract: This paper presents an open and fully Chisel-based hardware acceleration framework tailored for high-performance FPGA platforms, with a specific focus on AMD/Xilinx Alveo UltraScale+ cards. While the high-level synthesis (HLS) flow offered by Xilinx enables rapid deployment and is well-suited for many applications, it can be overly abstract for low-level control scenarios such as ASIC prototyping. The alternative RTL Kernel flow offers finer control but often suffers from the limitations of legacy hardware description languages and the overhead of vendor-specific tooling. To address these limitations, we propose a fully open-source workflow based on Chisel, a modern hardware construction language embedded in Scala. Chisel combines the flexibility of object-oriented programming with the ability to generate synthesizable RTL, enabling scalable, reusable, and modular designs. Our framework demonstrates how Chisel can be used to implement advanced hardware features including AXI4/AXI4-Lite interfacing, multi-clock domain designs, asynchronous communication primitives, and enhanced simulation capabilities such as custom VCD trace generation. The use of the Vivado RTL flow bypasses the constraints imposed by the Xilinx golden image and XRT stack, allowing direct programming and fine-grained control over the FPGA fabric. Lightweight host communication is achieved via the XDMA IP and Linux device files, enabling platform-agnostic integration using standard programming languages such as C++ and Python. As a proof of concept, we implement a high-throughput matrix-vector multiplication engine for floating-point data in a self-alignment format (SAF), fully utilizing the resources of a multi-SLR Alveo U200 card. Benchmark results show efficient pipelined operation and full cross-SLR scalability, validating the viability of the proposed framework for custom acceleration pipelines.