Near-Optimal Multirun March Memory Tests for Neighborhood Pattern-Sensitive Faults in Random-Access Memories

1. Introduction

As shown in the International Roadmap for Devices and Systems (IRDS) edited by the IEEE Computer Society or in works such as [1,2,3], in System on Chip (SoC) or Network on Chip (NoC), the memory part has a growing share, currently covering 75-85% of the integrated area. Therefore, in the production of reliable integrated circuits at competitive costs, efficient testing of the memory part is a very important requirement.

In this paper, the authors address the issue of testing $n\times 1$ RAMs with regard to the complex fault model of static unlinked neighborhood NPSFs, as a subclass of coupling faults (CFs) model [4,5]. According to the classification of memory faults, as presented for example in [2,6,7,8], the ‘static faults’ class refers to those faults sensitized by performing at most one memory operation, while the ‘dynamic faults’ class refers to those faults sensitized by two or more operations performed sequentially. According to the same taxonomy presented in [6] or [7], for example, CFs are said to be unlinked when they do not influence each other. In this paper, the class of static unlinked CFs is addressed.

The CF model reflects imperfections in the memory cell area that cause two or more cells to influence each other in their operation [2,3]. Depending on the number of cells involved in a memory fault, there are several classes of coupling faults, such as: two-cell coupling, three-cell coupling, four-cell coupling, or five-cell coupling. In the two-cell CF model, it is considered that the cells involved in a CF can be anywhere in the memory [9]. In this way, this model also covers addressing memory faults [6]. For more complex $k$-cell CF models, $k\ge 3$, it is assumed that the cells involved in a memory fault are physically adjacent [5,10,11]. It is therefore necessary to know the memory structure, or more precisely the correspondence between logical addresses and physical addresses, in the form of row and column addresses. This realistic limitation allows the complexity of these fault models to be more easily managed [12,13,14]. For these complex CF models, testing is usually done with additional integrated architectures, called built-in self-test (BIST) logic [15,16,17,18,19,20].

Regarding the $k$-cell CFs, depending on the technology used, the accuracy of the testing, and the costs involved, two classes of fault models have been defined to cover the most common memory errors, namely: (a) the classical model class in which it is considered that a memory fault can be sensitized only by a transition write operation, and (b) an extended class of models in which it is admitted that memory faults can be sensitized by transition write operations, as well as by non-transition writes or read operations – extended CF models (ECF) [9,12,13,14]. With the increase in density and the decrease in supply voltage, the range of memory defects has diversified, and as a result, for high testing accuracy, ECF models are increasingly used. The authors appreciate, however, that a memory test covering the classical CF model can be adapted relatively easily to cover the corresponding ECF model [12]. This is also highlighted in this work.

For three-cell or four-cell classical CF models, reference tests are reported in [10,11,21,22,23,24]. For three-cell or four-cell ECF models, near-optimal tests are presented in [14].

In this paper, we focus exclusively on the NPSF fault model involving five physically adjacent memory cells, arranged in a configuration like the one shown in Figure 1.

This NPSF fault model, which reflects the influence of neighboring cells on the central memory cell, has been defined since the 1970s [25]. Specifically, we refer here to the classical NPSF model in which a fault sensitization involves a transition write operation in one cell in the group, the other four cells being in a certain state that favors the occurrence of the memory error. The scientific community has continuously studied the NPSF model because of its importance and complexity. Memory testing for NPSF models is covered extensively in books, like [2,3,4,26], and in review papers, such as [16,17,19].

For the NPSF model, some memory tests have been proposed since the 1980s, that were quite effective for the memory sizes of that period [27,28]. For example, the memory test given by Suk and Reddy [28] is based on an algorithm for dividing the set of memory cells into two halves, based on row and column addresses, and is $165n$ long. A reduction in testing time was possible by applying march-type tests on different memory initialization patterns (data backgrounds). This idea was first proposed by Cockborn [23]. This technique, called ‘multirun march memory testing’, was then used to identify efficient memory tests for this complex NPSF model [29,30,31,32]. For example, in [31], to reduce the length of the test, Buslowska and Yarmolik propose a multirun technique with a random background variation. However, in that case, the NPSF model is not fully covered. A first near-optimal deterministic memory test for the NPSF model was proposed by Cheng, Tsai, and Wu in 2002 [32]. This memory test called $CM-79N$ is ${79}^{1/3}n$ long and uses 16 memory initialization patterns of size 3×3. Ten years later, Huzum and Cascaval [33] improved this result with another near-optimal memory test (called $March-76N$), slightly shorter, of length $76n.$Compared to the $CM-79N$, the $March-76n$memory test applies a different testing technique, but also uses 3×3 data background patterns. The $CM-79N$ and $March-76n$ tests are the shortest memory tests dedicated to this complex NPSF model. Although near-optimal, these tests are not exactly suitable for BIST implementation due to the complexity of the address-based data generation logic. More on this issue can be found in the works [34,35,36,37,38,39,40], but an in-depth analysis is also presented in this paper. For this reason, Cheng, Tsai and Wu also proposed in the same article [32] another memory test ($March-100N$) which, although longer (and obviously non-optimal), is easier to implement in BIST-RAM architectures due to its 4×4 memory initialization patterns. A modified version of the $March-100N$ memory test for diagnosis of SRAM is given by Julie, Sidek, and Wan Zuha [36].

In this work, a new near-optimal test ($MT\text{\_}NPSF\text{\_}81N$) able to cover the classical NPSF model is proposed. This new test is of length $81n$ and uses 16 data backgrounds with patterns of 4×4 in size, making it suitable for implementation in BIST-RAM architectures. Compared to the $March-100N$ test, this new memory test is significantly shorter and has a simpler structure. The synthesis of the address-based data generation logic for this memory test, considering a possible BIST implementation, is also discussed. This work also highlights the simplicity of address-based data generation logic in the case of 4×4 data backgrounds, compared to 3×3 ones. For the extended NPSF model (ENPSF), a near-optimal test of length $177n$ is proposed.

The remainder of this paper is organized as follows. Section 2 presents assumptions, notations, and some preliminary considerations related to multirun memory tests, or to the necessary and sufficient conditions for detecting memory coupling faults. Section 3 describes new near-optimal memory tests for the classical NPSF model and the extended NPSF one, respectively, that use 4×4 data background patterns. Section 4 presents a synthesis of data generation logic for memory operations, for a possible BIST implementation of the proposed memory tests. To emphasize the advantage of the proposed tests, compared to other known memory tests that use 3×3 background patterns, where modulo 3 residues are required for row and column addresses, an additional analysis showing the complexity of generating modulo 3 residues is presented in the Appendix. Section 5 completes the paper with some conclusions regarding this work.

2. Assumptions, Notations and Preliminaries

2.1. Assumptions

As in other works dedicated to NPSF models, it is assumed that the memory structure is fully known, so that based on the physical address information a multirun march test can be applied using different data backgrounds. Of course, in the memory, there can be one or more groups of coupled cells. As in other similar works, such as [4,26,30,31,32,33,34,35], it is assumed that the coupled cell groups are disjoint.

2.2. Notations

The notations used to describe memory operations or certain memory errors are shown below.

$r$	Operation of reading a memory cell and checking the value read by comparing it with the expected one.
$w_0\left(w_1\right)$	Operation of writing the logical value 0 (1) to the addressed cell.
$w_t$	Write operation to change the state of the addressed cell (transition write operation).
$w_{nt}$	Write operation without changing the state of the addressed cell (non-transition write operation).
$r^i,{w_{nt}^i,w}_t^i$, $w_0^i,w_1^i$	Memory operations with cell $i$.
$\uparrow$($\downarrow$)	A change of logical state in a memory cell from $0$to 1 ($1$to 0) by sensitizing a memory fault (i.e., a memory error).
$A_r\left(A_c\right)$	Row (column) address in a memory operation.
$v_i$	The logical value of memory cell $i$.

2.3. Preliminaries

A march memory test consists of a set of march items, each of them describing a sequence of operations that must be performed successively on all memory locations (moving to the next cell is done only after performing all operations on the current one). The first symbol of a march element specifies the order in which memory locations are accessed. Given a sequential enumeration of memory addresses, the symbol ⇑ indicates that these addresses are traversed in ascending order, while the symbol ⇓ indicates that they are traversed in reverse order.

In the case of multirun testing, a given march test is applied repeatedly on different data backgrounds. A data background is obtained by multiplying a data pattern in memory, both horizontally and vertically. Such a testing technique is currently used for any multi-cell CF model. Data backgrounds with row stripe, column stripe, or checkerboard patterns are commonly used in multirun-type memory testing [12,13]. For these data backgrounds the initialization patterns are of size 2×2. But the NPSF model we consider requires more complicated initialization patterns, concretely of size 3×3 or 4×4, as shown in [32,33], and as presented extensively in this work. Specifically, a data background pattern must completely cover the five-cell configuration shown in Figure 1 and, for this reason, the pattern must be at least 3×3 in size.

Generally, for a $k$-cell CF model, the affected cell (the cell where the memory error occurs) is considered $victimcell$ ($v-cell$) and the other $k-1$ cells in the group are considered to be $aggressorcells$ ($a-cells$) [7]. In order to describe more clearly how a memory fault is sensitized, sometimes the cell where the fault sensitizing operation is performed is considered to be the $aggressorcell$, and the other $k-2$ cells in the group which, by the state they are in, allow the appearance of the memory error, are called $enablingcells$ ($e-cells$) [6,7]. These aspects are illustrated in Figs 2 and 3. Since neighboring cells can exert a passive or active influence on the central cell, the NPSF model includes two types of faults, passive NPSF and active NPSF, as shown in Figure 2 and Figure 3, respectively [27,28].

Specifically, in the case of passive NPSF, a configuration of neighboring bits prevents a certain transition in the central cell, from 0 to 1 or from 1 to 0, as appropriate. In the case of an active NPSF, making a transition in one of the neighboring cells (aggressor cell), in a certain state of the other cells that facilitate the occurrence of the error (enabling cells), can cause the state to change in the central cell as well (↑ or ↓, as appropriate). The classical NPSF model comprises $2^5$ passive fault primitives and $4\times 2^5$ active fault primitives [41].

To detect a memory error, the test must sensitize the fault with a suitable transition write operation and then read the victim cell to observe the error. For the classical NPSF model, in terms of satisfying the sensitization condition of any fault, a memory test must entirely cover the state transition graph for any group of five cells in the known configuration.

Let $g=\{i,j,b,k,m\}$ be a group of five cells as shown in Figure 1, where $i<j<b<k<m$, which means that when memory addresses are traversed in ascending order (⇑), the cells are accessed in this order, and when memory addresses are traversed in descending order (⇓), the cells are accessed in the reverse order. Given this aspect, it can be said that a memory test is optimal if, for any group $g$ of cells, any transition write operation in the state graph is performed once and only once (i.e., for any group $g$ of cells, the state graph is Eulerian).

Considering the two types of NPSF faults (passive and active faults), as also mentioned in other works, e.g. [2,4,9,10], in order to detect any error resulting from memory fault sensitization, two necessary and sufficient observability conditions must be met:

${OC}_1$) A memory cell must be read after performing a fault sensitizing operation, prior to a new write, to verify that this operation was performed correctly.

${OC}_2$) Before writing to a cell, it must first be read, to verify that a state change has not occurred as a result of an operation previously performed in another possibly aggressor cell.

3. Near-Optimal March Tests for the NPSF Model

To cover the classical NPSF model, where a fault sensitization involves a transition write operation in a cell of the coupled cell group with the configuration shown in Figure 1, a new memory test is proposed, called $MT\text{\_}NPSF\text{\_}81N$. In this test, two march elements are applied sixteen times on different data backgrounds (i.e., a multirun technique). The description of this new march multirun memory test is given in Figure 4, and the sixteen patterns used for memory initialization are shown in Figure 5.

In this description,${BGC}_1$ indicates the primary memory initialization sequence while ${BGC}_i$, $i\in \left\{2,3,\dots ,16\right\}$, represent test sequences with background changes, according to the patterns shown in Figure 5. Note that, any change of data background involves a status update only for half of the memory cells. On the other hand, in order to satisfy the ${OC}_2$ observability condition, any write operation to change the state of a memory cell is preceded by a read operation. Thus, the initialization sequence ${BGC}_1$, which is of the form $\Uparrow \left(w_0\right)$, involves $n$ write operations, while a test sequence with background change, ${BGC}_i$, $i\in \left\{2,3,\dots ,16\right\}$, requires $n/2$ read operations and $n/2$ write operations. Thus, the length of the memory test is:

$$\mathcal{L}=n+4n+15\times \left(1+4\right)n+n=81n.$$

(1)

The ability of the $MT\text{\_}NPSF\text{\_}81N$ memory test to cover the NPSF model is discussed in the following.

Theorem 1

. The $MT\text{\_}NPSF\text{\_}81N$ test algorithm is able to detect all unlinked static faults of this classical NPSF model.

$Proof:$ Let $g$ be an arbitrary group of five neighboring memory cells corresponding to the well-known NPSF configuration shown in Figure 1. Considering the order in which these cells are accessed on a memory scan in ascending address order, cells in group $g$ are denoted by $i$, $j,b,k,$ and $m$, as illustrated in Figure 1.

The ability of the $MT\text{\_}NPSF\text{\_}81N$ test algorithm to sensitize and observe any fault that may affect a cell in a cell group $g=\{i,j,b,k,m\}$ is demonstrated in the following.

$$\mathrm{I}.MT\text{\_}NPSF\text{\_}81N \mathrm{is} \mathrm{a}\mathrm{b}\mathrm{l}\mathrm{e} \mathrm{t}\mathrm{o} \mathrm{s}\mathrm{e}\mathrm{n}\mathrm{s}\mathrm{i}\mathrm{t}\mathrm{i}\mathrm{z}\mathrm{e} \mathrm{a}\mathrm{n}\mathrm{y} \mathrm{f}\mathrm{a}\mathrm{u}\mathrm{l}\mathrm{t} \mathrm{i}\mathrm{n} \mathrm{a} g-\mathrm{g}\mathrm{r}\mathrm{o}\mathrm{u}\mathrm{p} \mathrm{o}\mathrm{f} \mathrm{c}\mathrm{o}\mathrm{u}\mathrm{p}\mathrm{l}\mathrm{e}\mathrm{d} \mathrm{c}\mathrm{e}\mathrm{l}\mathrm{l}\mathrm{s}$$

To prove this statement, it is shown that during the memory testing, $MT\text{\_}NPSF\text{\_}81N$performs all possible operations in the group of cells $g=\{i,j,b,k,m\}$. In other words, $MT\text{\_}NPSF\text{\_}81N$completely covers the graph of states describing the normal functioning of cells in this group.

Given that the test uses 4×4 memory initialization patterns, it follows that the cells selected 4 by 4 per row or column are brought to the same initial state and, consequently, the same operations are then performed on them during the application of a march element. Starting from this observation, the memory cells are divided into 16 classes (subsets), $C_1,C_2,\dots ,C_{16},$ depending on the residues of the row address modulo 4 ($A_r\mathrm{m}\mathrm{o}\mathrm{d}4$) and the column address modulo 4 ($A_c\mathrm{m}\mathrm{o}\mathrm{d}4$), as shown in the following table (Table 1).

This division of the memory cell set into 16 classes according to row and column addresses is illustrated in Figure 6.

Let now $G_i$ be the subset of all $g$-groups of five cells in the known configuration for which the base cell ${b\in C}_i,i\in \left\{1,2,\dots ,16\right\}$. This class division of the $g$-groups of five cells is also illustrated in Figure 6. This figure shows that the cells in the neighborhood of the base cells also belong to the same classes. For example, for the groups of cells in the subset $G_6$, the cells identified with $i$belong to $C_2$, those identified with $j$ belong to $C_5$, and so on.

In the following, let us analyze the initial state for a group $g$ of five memory cells in the known configuration, depending on the data background $\left(\mathrm{B}\mathrm{G}1-\mathrm{B}\mathrm{G}16\right)$ and the class of groups it belongs to $\left(G_1-G_{16}\right)$.

The status code for a group of cells is a word that includes the five logical values ​​of the component cells, in the form $v_i{v}_j{v}_b{v}_k{v}_m$. It is worth noting that a group $g$ of cells in the state $S=v_i{v}_j{v}_b{v}_k{v}_m$ will reach the complementary state $S^{\prime }=\overline{v_i}\overline{v_j}\overline{v_b}\overline{v_k}\overline{v_m}$ when the march element $\Uparrow \left(r{w}_t\right)$ is applied. We say that $S$ and $S^{\prime }$ are complementary states because for any pair $S$ and $S^{\prime }$ the following relation holds:

$$S+S^{\prime }={11111}_{\mathrm{B}}=\left({1\mathrm{F}}_{\mathrm{H}}\right).$$

(2)

Figure 7 illustrates the initial and complementary states, $I_x$and $I_x^{\prime }$, for two groups of cells depending on data background, BG$x,x\in \left\{1,2,\dots ,16\right\}$, namely $G_1$ and$G_{11}.$The initial state and the complementary one for a group of cells in the known configuration, depending on the initialization pattern $\left(\mathrm{B}\mathrm{G}1,\mathrm{B}\mathrm{G}2,\dots .,\mathrm{B}\mathrm{G}16\right)$ and the class of which the group belongs $\left(G_1,G_2,...,G_{16}\right)$, are presented in Table 2. In this table, it can be verified that for any group $g$ of five neighboring cells in the known configuration, regardless of the class to which the group belongs (i.e., any column), the 16 background changes result in 16 distinct initial states, such that

$$I_x\ne I_y,\forall x,y\in \left\{1,2,\dots ,16\right\},x\ne y$$

(3)

Furthermore, for any column in Table 2, the following equation is valid:

$$I_x\ne I_y^{\prime },\forall x,y\in \left\{1,2,\dots ,16\right\}$$

(4)

If $\mathcal{S}$ represents the set of all $2^5=32$states (as in the truth table), based on (3) and (4) we can write:

$$\bigcup _{x=1}^{16}\left(I_x\cup I_x^{\prime }\right)=\mathcal{S}.$$

(5)

Note that the states in any of the 16 columns of Table 2 satisfy equation (5), which means that all initial states and their complementary ones are different from each other and all together form the set $\mathcal{S}$.

As a remark, identifying those initialization models for which this property is fulfilled has involved a considerable research effort.

It is also important to note that, starting from an initial state $I_x,x\in \left\{1,2,\dots ,16\right\}$, upon execution of the first march element (of the form $\Uparrow \left(r{w}_t\right)$), a group$g$ of cells is brought to the complementary state $I_x^{\prime }$, and after the next march element (identical to the first), that group of cells is returned to the initial state $I_x$.

Based on all these aspects, we can conclude that any group $g$ of cells in the known configuration is brought into each of the 32 possible states, and then a march element of the form $\Uparrow \left(r{w}_t\right)$ is applied.

In a full memory scan with the march element $\Uparrow \left(r{w}_t\right)$, 5 different transitions are performed in any group of five cells. On the whole, in a group of five cells, $32\times 5=160$ transitions are performed. For example, Figure 8 shows the transitions performed in a group $g$ of cells of class $G_1$ in the first 6 of the 16 stages of the memory test. The initial states after the 6 background changes are highlighted in bold. For easier identification, the transitions performed at each iteration are shown in different colors, and for the first transition within an iteration, an identification number is written on the edge.

Next, it is shown that all 160 transitions performed in a group $g$ of cells are different transitions and therefore the state transition graph is completely covered.

Figure 9 shows the evolution of the states for a group of cells $g=\{i,j,b,k,m\}$, starting from two different initial states, $I_{x_0}$ $\ne$ $I_{y_0}$, when the march element $\Uparrow \left(r{w}_t\right)$ is applied. The intermediate states that appear in the figure, $I_{x_u}$ and $I_{y_u}$, $u=1,2,3,4,$ are detailed in Table 3.

From Table 3, it follows that, since $I_{x_0}\ne I_{y_0}$, $I_{x_u}\ne I_{y_u},u\in \left\{1,2,3,4\right\}.$ Note that although often$I_{x_u}=I_{y_v}$, $u\ne v,$ in the two cases, the write operations are performed on different memory cells and therefore the respective transitions are also different. Several such cases are found in Figure 8, such as the transitions made in the states 10000, 10100, 10010 or 01001.

In conclusion, by applying the $MT\text{\_}NPSF\text{\_}81N$memory test, $16\times 2\times 5=160$ different transitions are performed in the $g$-group of cells, completely covering the state transition graph. Moreover, each of these transitions is performed only once. As a result, the sensitization condition for all coupling faults specific to this classical NPSF model is met.

$\mathrm{I}\mathrm{I}.MT\text{\_}NPSF\text{\_}81N\mathrm{d}\mathrm{e}\mathrm{t}\mathrm{e}\mathrm{c}\mathrm{t}\mathrm{s}\mathrm{a}\mathrm{n}\mathrm{y}\mathrm{s}\mathrm{e}\mathrm{n}\mathrm{s}\mathrm{i}\mathrm{t}\mathrm{i}\mathrm{z}\mathrm{e}\mathrm{d}\mathrm{f}\mathrm{a}\mathrm{u}\mathrm{l}\mathrm{t}\mathrm{i}\mathrm{n}\mathrm{a}\mathrm{g}\mathrm{r}\mathrm{o}\mathrm{u}\mathrm{p}g\mathrm{o}\mathrm{f}\mathrm{c}\mathrm{o}\mathrm{u}\mathrm{p}\mathrm{l}\mathrm{e}\mathrm{d}\mathrm{c}\mathrm{e}\mathrm{l}\mathrm{l}$

Proving this property involves verifying the fulfillment of the two observability conditions, ${OC}_1$ and ${OC}_2$, presented in Section 2. For an easier and more direct verification of the fulfillment of the observability conditions, Figure 10 shows all the operations performed in a group of cells $g=\left\{i,j,b,k,m\right\}$ during the execution of the $MT\text{\_}NPSF\text{\_}81N$memory test. In the sequence of operations performed on cells in group $g$, write operations for initialization or background change are written in normal font, and those with the role of memory fault sensitization are highlighted in blue. Read operations that have the role of detecting possible errors resulting from fault sensitization are written in red.

Analyzing the sequence of operations shown in Figure 10, it can be seen that when a cell is accessed, it is first read, thus checking whether a state change has occurred in the cell, as a result of an influence from another aggressor cell. This check is required by condition ${OC}_2$. Also, by analyzing the sequence of operations illustrated in this figure, it can be seen that after performing a write operation on a cell, it is then read (immediately or later) to verify that the operation was performed correctly. Thus, condition ${OC}_1$ is also met.

With the verification of both conditions regarding the sensitization of all considered memory faults and the ability to detect any resulting errors, the proof of the theorem is complete. ?

Remark 1.

For any group of cells that corresponds to the considered NPSF model, the state transition graph is completely covered, and furthermore, each transition is performed only once. That means that the graph of states is Eulerian. The only redundant operations are used for background changes. With this argument, it can be said that this memory test is near-optimal.

The proposed memory test can be adapted to cover the extended NPSF model (ENPSF), in which memory faults can be sensitized by transition write operations but also by read or non-transition write operations [41]. To this end, the two march elements of form $\Uparrow \left({r,w}_t\right)$are extended to the form $\Uparrow \left({r,w_{nt},r,r,w}_t\right)$. This extension leads to a near-optimal memory test for the ENPSF model, called $MT\text{\_}ENPSF$, of length $177n$, as shown in Figure 11.

Note that in this case, when a certain state is reached, the $w_{nt}$and $r$ operations are first executed and checked, and then the state is changed by a $w_t$ operation.

Remark 2.

The ability of each of the two memory tests to cover the considered NPSF model was also verified by simulation. In the case of faults sensitized by transition write operations, the TRAP interrupt was used to simulate memory errors. For the other memory faults, dedicated simulation programs were required.

Remark 3.

The proposed tests, $MT\text{\_}NPSF\text{\_}81N$ and $MT\text{\_}ENPSF$, also cover the three-cell CF model involving neighboring memory cells arranged in a corner or on a row or column [5,10,11,12,13,14], in the classical and extended versions, respectively, since the three-cell configurations are included in the five-cell one.

4. Considerations for BIST Implementation of the Proposed Memory Tests

In this section, a possible synthesis of the data generation logic for memory operations is discussed, considering a possible BIST implementation of the proposed memory test. Specific to such a multirun test is the dependency between the value of a memory cell and its address. It should be noted that 4×4 background patterns allow for a simple synthesis of data generation logic. This is due to the fact that the logical value for the current cell is generated based on the two least significant bits (LSB) of the row address, $A_r\left[1\right]$and $A_r\left[0\right]$, and/or the column address, $A_c\left[1\right]$and $A_c\left[0\right]$. Table 4 presents a possibility of generating data based on the address depending on data background. The memory initialization patterns are taken into the table for easier verification.

The MT_NPSF_81N memory test repeats two march elements 16 times, on different background patterns. Consequently, in order to adapt the logical value of the accessed cell to the background, a test sequence counter $\left(TSC\right)$ of length 4 and a 16-input multiplexer are required. Considering the relationships between date and address depending on the data background, as presented in Table 4, a possible solution for the data generation logic is shown in Figure 12.

The $Invert$ command that appears in the data generation logic, provided by the control logic, is required to perform transition write operations in the first memory scan and read operations in the second, as highlighted in blue in this test sequence: $\Uparrow \left(r{w}_t\right);\Uparrow \left(r{w}_t\right)$.

This synthesis shows that the $MT\text{\_}NPSF\text{\_}81N$ memory test, despite using a large number of initialization patterns with some irregular structures, can be implemented quite easily in BIST-RAM architectures.

For comparison, let us analyze the possibility of implementing in self-testable structures the other two near-optimal memory tests dedicated to this classical NPSF model reported so far, $CM-79N$ [33] and $March-76N$ [34], which are somewhat shorter but use memory initialization patterns of size 3×3. In a memory test using 3×3 background patterns, the address-based data generation requires generating the modulo 3 residues of the row and column addresses. But this is a very complicated issue. The difficulty of hardware generation of modulo 3 residues is highlighted in the Appendix. This is the major disadvantage of memory tests that use 3×3 data background patterns. For this reason, the authors argue that the new $MT\text{\_}NPSF\text{\_}81N$ memory test, although slightly longer, is more suitable for implementation in self-testing RAM structures, compared to the other two known near-optimal memory tests, $CM-79N$ and $March-76N$.

5. Conclusion

The paper proposes two near-optimal memory tests dedicated to the complex NPSF model, both in the classic version in which it is accepted that a fault is only sensitized by a transition write operation, and in the extended version in which faults sensitized by a non-transition write or a read operation are also taken into account. The proposed tests, $MT\text{\_}NPSF\text{\_}81N$ and $MT\text{\_}ENPSF$, respectively, are multirun march memory tests that use 4×4 data background patterns and are specifically designed to be easy to implement in self-testing RAM architectures. These are the first near-optimal memory tests dedicated to the NPSF model using 4×4 data initialization patterns reported to date.

Due to the difficulty of generating modulo 3 residues for row and column addresses (an aspect highlighted in detail in the appendix), the authors state that memory tests using 3×3 memory initialization patterns (as are the other two known near-optimal tests for the classical NPSF model, $CM-79N$ and $March-76N$) are not exactly suitable for implementation in self-testing RAM structures.

The evaluation of the optimality of the proposed tests is based on the fact that, for any group of cells corresponding to the NPSF model, the state graph is completely covered, and each arc is traversed only once, which means that the graph is Eulerian. Some additional memory write operations are only required for background changes. All these aspects were also verified through simulation.

The memory initialization patterns were designed so that any group of five cells in the known configuration would be brought into each of the 32 possible states, only once. A great deal of research effort was required to fulfill this condition. The authors identified this optimal solution intuitively, but in future research they will try to identify other solutions through search methods specific to artificial intelligence.