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Serverless Architecture and Its Current State of the Art: A Systematic Literature Review
Ammad Ul Haq Farooqi
,Omer Khalid
,Muhammad Bilal
Posted: 04 December 2025
Production Development with Microservices Architecture and DevOps Practices
David Ostapchenko
Posted: 01 December 2025
Garbage Collection in Node.js: How Memory Management Affects Application Performance
Parvani Vafa Mokhammad
Posted: 01 December 2025
An Empirical Comparison of Microservice and Monolithic Architectures in Software Development
Saikal Batyrbekova
Posted: 17 November 2025
Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead
Guang Yang
,Wei Zheng
,Xiang Chen
,Dong Liang
,Peng Hu
,Yukui Yang
,Shaohua Peng
,Zhenghan Li
,Jiahui Feng
,Xiao Wei
+7 authors
Code generation has emerged as a critical research area at the intersection of Software Engineering (SE) and Artificial Intelligence (AI), attracting significant attention from both academia and industry. Within this broader landscape, Verilog, as a representative hardware description language (HDL), plays a fundamental role in digital circuit design and verification, making its automated generation particularly significant for Electronic Design Automation (EDA). Consequently, recent research has increasingly focused on applying Large Language Models (LLMs) to Verilog code generation, particularly at the Register Transfer Level (RTL), exploring how these AI-driven techniques can be effectively integrated into hardware design workflows. Despite substantial research efforts have been invested to explore LLM applications in this domain, a comprehensive survey synthesizing these developments remains absent from the literature. This review fill addresses this gap by providing a systematic literature review of LLM-based methods for Verilog code generation, examining their effectiveness, limitations, and potential for advancing automated hardware design. The review encompasses research work from conferences and journals in the fields of SE, AI, and EDA, encompassing 70 published papers, along with 32 high-quality preprint papers, bringing the total to 102 papers. By answering four key research questions, we aim to (1) identify the LLMs used for Verilog generation, (2) examine the datasets and metrics employed in evaluation, (3) categorize the techniques proposed for Verilog generation, and (4) analyze LLM alignment approaches for Verilog generation. Based on our findings, we have identified a series of limitations of existing studies. Finally, we have outlined a roadmap highlighting potential opportunities for future research endeavors in LLM-assisted hardware design.
Code generation has emerged as a critical research area at the intersection of Software Engineering (SE) and Artificial Intelligence (AI), attracting significant attention from both academia and industry. Within this broader landscape, Verilog, as a representative hardware description language (HDL), plays a fundamental role in digital circuit design and verification, making its automated generation particularly significant for Electronic Design Automation (EDA). Consequently, recent research has increasingly focused on applying Large Language Models (LLMs) to Verilog code generation, particularly at the Register Transfer Level (RTL), exploring how these AI-driven techniques can be effectively integrated into hardware design workflows. Despite substantial research efforts have been invested to explore LLM applications in this domain, a comprehensive survey synthesizing these developments remains absent from the literature. This review fill addresses this gap by providing a systematic literature review of LLM-based methods for Verilog code generation, examining their effectiveness, limitations, and potential for advancing automated hardware design. The review encompasses research work from conferences and journals in the fields of SE, AI, and EDA, encompassing 70 published papers, along with 32 high-quality preprint papers, bringing the total to 102 papers. By answering four key research questions, we aim to (1) identify the LLMs used for Verilog generation, (2) examine the datasets and metrics employed in evaluation, (3) categorize the techniques proposed for Verilog generation, and (4) analyze LLM alignment approaches for Verilog generation. Based on our findings, we have identified a series of limitations of existing studies. Finally, we have outlined a roadmap highlighting potential opportunities for future research endeavors in LLM-assisted hardware design.
Posted: 13 November 2025
An Imperative Term Graph Programming Language
David A. Plaisted
Posted: 05 November 2025
Validating a First Educational Training System to Teach ScratchJr to Neurotypical and Neurodivergent Children According to Their Preferences and Needs
María Jesús Manzanares
,Diana Pérez-Marín
,Celeste Pizarro
Posted: 05 November 2025
rUnit—A Framework for Test Analysis of C Programs
Peter Backeman
Posted: 29 October 2025
DEVS Closure Under Coupling, Universality, and Uniqueness: Enabling Simulation and Software Interoperability from a System-Theoretic Foundation
Bernard Zeigler
,Robert Kewley
,Gabriel Wainer
Posted: 15 October 2025
Systems Interoperability for Pandemic Response: Evidence from the Philippines’ COVID-19 Management
Philip Christian Zuniga
,Rose Ann Zuniga
,Marie Jo-anne Mendoza
,Ada Angeli Cariaga
,Prometheus Lazo
,Czaezarina Calimbahin
,Kristin Chloe Balbas
,Raymond Francis Sarmiento
Posted: 01 October 2025
Wise and Complex Enterprise Architecture for FMIS
Sara BourBour
,Mohammad Reza Besharati
Posted: 15 September 2025
EPT Switching vs. Instruction Repair vs. Instruction Emulation: A Performance Comparison of Hyper-Breakpoint Variants
Lukas Beierlieb
,Alexander Schmitz
,Anas Karazon
,Artur Leinweber
,Christian Dietrich
Posted: 15 September 2025
Model for the Adoption of AI Tools in the Software Development Life Cycle: A Framework for Prompt Optimization in LLMs
Vania Linette Méndez Morales
,José Manuel Gómez Zea
,José Ángel Jesús Magaña
,Teresa De Jesús Javier Baeza
,Alejandro Hernández Cadena
,Jonathan de la Cruz Álvarez
Posted: 12 September 2025
Modeling Continuous-Electrode Magnetohydrodynamic Channels with a Demonstration through the “Sakhalin” Generator
Osama A. Marzouk
Posted: 09 September 2025
Design and Optimization of Low Power Persistent Logging System Based on Embedded Linux
Caiwei Wu
,Fengrui Zhang
,Huangyin Chen
,Junlin Zhu
Posted: 03 September 2025
Design and Implementation of Cross-Platform Fault Reporting System for Wearable Devices
Caiwei Wu
,Huangyin Chen
,Junlin Zhu
,Yao Yao
Posted: 03 September 2025
Identifying and Optimizing Performance Bottlenecks of Logging Systems for Augmented Reality Platforms
Caiwei Wu
,Junlin Zhu
,Yao Yao
Posted: 03 September 2025
Research on System Service Convergence Architecture for AR/VR System
Caiwei Wu
,Huangyin Chen
Posted: 03 September 2025
Secure Engineering of Autonomous AI Agents: A Threat-Driven Development Framework
Tanvir Ahmed
,Samiul Hasan
,Ahammed Shorif
,Ansarul Hoque
,Shadman Sajid
,Md. Badiuzzaman Biplob
Posted: 14 August 2025
Securing the Software Development Lifecycle with Large Language Models: A Framework for Automated Threat Modeling and Secure Code Generation
Shuvo Chakraborty
,Mehedi Hassan
,Habibullah Mohammad Masum
,Md Rakibul Islam Fahim
,Sayed Mahmood Twki
,Md. Badiuzzaman Biplob
Posted: 11 August 2025
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