Memristor has attracted a lot of interest due to its high processing speed, low power consumption and high integration ability, which is critical for electronic systems and memory-centric computing. However, the memristor programming circuit and strategy are still inflexible and complex, since the signal generator/collector and stimulate pulse must be carefully matched and designed based on memristor intrinsic characteristics without reconfigurable. Here, a simple and effective circuit only consists a parallel reference-resistor-and-NMOS is designed to program memristor with a more than 99% memristance precision. And the amplitude and width of stimulate pulse are fixed to ±4V and 5ms, respectively. In order to cope with the device variation, such as ±10% tolerance of transition voltage, an optimized programming strategy was proposed and demonstrated great robustness. Additionally, a set of reference resistors and NMOSs have been added to facilitate multi-level memristance operation without requiring any changes to the circuit structure. This program circuit was also employed to program memristor crossbar remains 99% precision. In the end, a memristor-based convolutional neural network which controlled by our optimized programming circuit was used for image recognition, and 89.36% accuracy can be achieved even under 15.8% memristance tolerance. This novel circuit demonstrates a simple and flexible strategy in memristor programming, providing a new way to control memristor crossbar for practical application.

This study systematically addresses the challenge of accurately modeling memristors, focusing on four distinct types doped with tungsten, tin, chromium, and carbon, fabricated by Known Inc. A comprehensive characterization was performed by subjecting the devices to sinusoidal excitations with varying frequencies and amplitudes, followed by data averaging and high-frequency filtering. The resulting measurements were fitted using three prominent memristor models: VTEAM, MMS, and Yakopcic, with additional bespoke modifications assessed. These models, typically formulated as coupled algebraic-differential equations integrating electrical quantities (voltage and current) with internal state variables governing device dynamics, were optimized using two robust approaches: (1) interior-point optimization with gradient-based search, and (2) Nelder-Mead gradient-free optimization, both with box constraints applied. A thorough comparison and discussion of the optimized model parameters ensued, accompanied by an examination of sensitivity to diverse frequency and amplitude ranges. The findings inform conclusions and provide a foundation for future refinements, underscoring the importance of multi-model evaluation and advanced optimization strategies in precise memristor modeling. The presented methodology offers a valuable framework for elucidating optimal modeling paradigms tailored to specific memristor architectures and operating regimes, ultimately enhancing their integration in emerging neuromorphic and computational applications.

Principle of memristor presented by Leon Chua and time reversal based non-linear elastic wave spectroscopy (TR-NEWS) which can be applied to acoustic tomography are reviewed. Correlation of acoustic or electromagnetic nonlinear waves and its time reversed wave can produce strong signal. Materials like transducer or biological skin can be assumed to be composed of a large number of small elastic unit: hysteretic elementary unit (HEU), and one can take a HEU as a memristor whose operation depends on time. Relation between TR-NEWS and solitonic wave in fluid, and relation between decomposition of time reversal operator (DORT) and chaotic oscillation are discussed.

Memristors are state-of-the-art, nano-sized, two-terminal, passive electronic elements with very good switching and memory characteristics. Owing to their very low power usage and a good compatibility to the existing CMOS ultra-high-density integrated circuits and chips, they are po-tentially applicable in artificial and spiking neural networks, memory arrays, and many other de-vices and circuits for artificial intelligence. In this paper, a complete electronic realization of ana-log circuit model of modified neural net with memristor-based synapses and transfer function with memristors and MOS transistors in LTSPICE is offered. Each synaptic weight is realized by only one memristor, providing enormously reduced circuit complexity. The summing and scaling implementation is founded on op-amps and memristors. The logarithmic-sigmoidal activation function is based on a simple scheme with MOS transistors and memristors. The functioning of the suggested memristor-based neural network for pulse input signals is evaluated both analytically in MATLAB-SIMULINK and in LTSPICE environment. The obtained results are compared one to another and are successfully verified. The realized memristor-based neural network is an im-portant step towards the forthcoming design of complex memristor-based neural networks for ar-tificial intelligence, for implementation in very high-density integrated circuits and chips.

Analog neuromorphic prototyping is crucial for creating spiking neuron models that use memristive devices as synapses to design integrated circuits that leverage on-chip parallel deep neural networks. These models mimic how biological neurons in the brain communicate through electrical potentials. Doing so enables more powerful and efficient functionality than traditional artificial neural networks that run on von Neumann computers or graphic processing unit-based platforms. This technology can accelerate deep learning processing, aiming to exploit the brain’s unique features of asynchronous and event-driven processing by leveraging neuromorphic hardware’s inherent parallelism and analog computation capabilities. Therefore, this paper presents the design and implementation of a leaky integrate and fire neuron prototype implemented with commercially available components on a PCB board. Simulations conducted in LTSpice agree well with the electrical test measurements. The results demonstrate that this design can be employed to interconnect many boards to build layers of physical spiking neurons, interconnected with spike-timing-dependent plasticity as the primary learning algorithm, contributing to the realization of experiments in the early stage of adopting neuromorphic computing.

This article presents a novel computational approach to visualizing memristor dynamics within a simulated neural network. Memristors, known for their ability to emulate synaptic plasticity due to their variable resistance characteristics, are key components in neuromorphic computing and hold potential for advancing our understanding of neural processes. Our study introduces a sophisticated memristor model that incorporates non-linear resistance changes, simulating the complex behavior of synaptic connections in a neural network.The neural network, consisting of multiple interconnected neurons with memristor-based synapses, is subjected to a series of electrical stimuli. Each memristor's resistance is modulated in response to the applied voltage, mimicking the synaptic weight adjustments that occur during learning and memory formation in biological neural networks. To effectively illustrate these changes, we employ a high-contrast color mapping scheme, where the varying resistance of each memristor is represented by distinct colors, providing a clear and intuitive visualization of synaptic modifications over time.Our simulation runs through multiple iterations, demonstrating how synaptic weights evolve in response to different input patterns. The use of an extended voltage range and increased scaling factors ensures pronounced changes in memristance, enhancing the visibility of synaptic adaptations. The resulting visualizations offer a compelling representation of how memristors can mimic the dynamic nature of biological synapses, contributing to the field of neuromorphic engineering and deepening our comprehension of neural mechanisms underlying learning and memory.This work not only showcases the potential of memristors in simulating neural behavior but also provides a valuable educational tool for illustrating complex concepts in neuroscience and neuromorphic computing. The insights gained from this study pave the way for further exploration into the development of advanced neural network models and the design of memristor-based computing systems.

Multiply-accumulate calculations using a memristor crossbar array is an important method to realize neuromorphic computing. However, the memristor array fabrication technology is still immature, and it is difficult to fabricate large-scale arrays with high-yield, which restricts the development of memristor-based neuromorphic computing technology. Therefore, cascading small-scale arrays to achieve the neuromorphic computational ability that can be achieved by large-scale arrays, which is of great significance for promoting the application of memristor-based neuromorphic computing. To address this issue, we present a memristor-based cascaded framework with some basic computation units, several neural network processing units can be cascaded by this means to improve the processing capability of the dataset. Besides, we introduce a split method to reduce pressure of input terminal. Compared with VGGNet and GoogLeNet, the proposed cascaded framework can achieve 93.54% Fashion-MNIST accuracy under the 4.15M parameters. Extensive experiments with Ti/AlOx/TaOx/Pt we fabricated are conducted to show that the circuit simulation results can still provide a high recognition accuracy, and the recognition accuracy loss after circuit simulation can be controlled at around 0.26%.

Memristors were proposed in the early ’70s of the XXth century by Leon Chua as a new electrical element linking the charge and the flux. Since that first introduction, these devices have positioned themselves to be considered as possibly fundamental for the new generations of electronic devices. It has to be mentioned that actual memristors have only been recognized to exist as physical elements. In this paper, we apply a modeling framework to generate a model describing experimental measurements performed on a ReRAM. We show how to apply the Dynamic Route Map technique in the general case to obtain an approximation to the differential equation that determines the behaviour of the device.

In this paper, a system of searching for optimal paths is developed and concreted on a FPGA. It is based on a memristive emulator, used as a delay element, by configuring the test graph as a memristor network. A parallel algorithm is applied to reduce computing time and increase efficiency. The operation of the algorithm in Matlab is checked beforehand and then exported to two different Intel FPGAs: a DE0-Nano board and an Arria 10 GX 220 FPGA. In both cases reliable results are obtained quickly and conveniently, even for the case of a 300x300 nodes maze.

Because the development of the internet of things (IoT) requires technology that transfers information between objects without human intervention, the core of IoT security will be secure authentication between devices or between devices and servers. Software-based authentication may be a security vulnerability in IoT, but hardware-based security technology can provide a strong security environment. A physical unclonable functions (PUFs) are a hardware security element suitable for lightweight applications. PUFs can generate challenge-response pairs(CRPs) that cannot be controlled or predicted by utilizing inherent physical variations that occur in the manufacturing process. In particular, pulse width memristive PUF (PWM-PUF) improves security performance by applying different write pulse widths and bank structures. Bloom filter (BF) is probabilistic data structures that answer membership queries using small memories. Bloom filter can improve search performance and reduce memory usage and are used in areas such as networking, security, big data, and IoT. In this paper, we propose a structure that applies Bloom filters based on the PWM-PUF to reduce PUF data transmission errors. The proposed structure uses two different Bloom filter types that store different information and that are located in front of and behind the PWM-PUF, improving security by removing challenges from attacker access. Simulation results show that the proposed structure decreases the data transmission error rate and reuse rate as the Bloom filter size increases, the simulation results also show that the proposed structure improves PWM-PUF security with a very small Bloom filter memory.

In this article, we propose a circuit to imitate the behavior of a Reward-Modulated Spike-Timing-Dependent Plasticity synapse. When two neurons in adjacent layers produce spikes, each spike modifies the thickness of the common synapse. As a result, the synapse’s ability to conduct impulses is controlled, leading to an unsupervised learning rule. By introducing a reward signal, reinforcement learning is enabled by redirecting the growth and shrinkage of synapses based on signal feedback from the environment. The proposed synapse manages the convolution of the emitted spike signals to promote either the strengthening or weakening of the synapse, which is represented as the resistance value of a memristor device. As memristors have a conductance range that may differ from the available current input range of typical CMOS neuron designs, the synapse circuit can be adjusted to regulate the spike’s amplitude current to comply with the neuron. The circuit described in this work allows for the implementation of fully interconnected layers of neuron analog circuits. This is achieved by having each synapse reconform the spike signal, thus removing the burden of providing enough power from the neurons to each memristor. The synapse circuit was tested using a CMOS analog neuron described in the literature. Additionally, the article provides insight into how to properly describe the hysteresis behavior of the memristor in Verilog-A code. The testing and learning capabilities of the synapse circuit are demonstrated in simulation using the Skywater-130nm process. The article’s main goal is to provide the basic building blocks for Deep Neural Neural Networks relying on spiking neurons and memristors as the basic processing elements to handle spike generation, propagation, and synaptic plasticity.

In the last years, advances in materials engineering based on adaptive electronics have found a new paradigm to optimize drawbacks in signal processing. A two-layer MnO/ZnO:Zn heterostructure envisioned for frequency adaptive electronic signal processing is synthesized by sputtering where the use of internal states allows reconfigurability to obtain new operating modes at different frequency input signals. An X-Ray Diffraction (XRD) is performed on each layer, MnO:Mn had a cubic and ZnO:Zn a hexagonal structure with preferential growth in [111] and [002] directions respectively. It is determined that the coupling in this heterojunction is compatible with a mismatch less 1 % due texture in each layer which implies a low number of defects. An electrical characterisation with an oscilloscope and signal generator was carried out to obtain the time-response signals and current-voltage (I-V) curves where no degradation is detected when changing from a range of frequencies (100 Hz – 1 MHz). An equivalent circuit is proposed to explain the effects in the interface. Finally, the MnO/ZnO:Zn heterojunction delivers states that are stable, repeatable, and reproducible and it demonstrates how the interaction of the materials can be used in adaptive device applications applying frequencies and internal states as to create new and innovative design schematics, reducing the numbers of components/connections in a system for future sustainable electronics.

We observed and studied the phenomenon of the redox front propagation in different polyaniline (PAni) deposited samples interfaced with liquid or solid polymeric electrolyte. The front of electrochemical conversion, in which the insulator and the conductor parts of PAni are interfaced, is studied observing the temporal evolution of the conductivity of PAni samples. The propagation of redox front was studied in electrochemically obtained thick (2 µm) and in thin (50 nm) poly-aniline films, obtained using Langmuir-Blodgett (LB) method. In the configuration that we tested, the speed of the red-ox front propagation for the thin LB films was found to be 200 micron/sec opening the way for the manufacturing large neural networks, realized using PAni based memristive devices, in which the memristance can be quickly changed in the programmable manner. The prototypes of the spiking neuron connections were manufactured on the basis of lithographically developed gold contacts, bridged by electrochemically grown polyaniline and placed under polymer electrolyte layer with only one counter electrode (gate) for the whole manifold of pseudo-two-terminal memristor bridges. The spike propagation was studied in such gold-polyaniline systems. The research opens the possibility of miniature spike or rate-based neural network circuits manufacture, based on metal pads and polyaniline.

Due to the increased use of memristors, and its many applications, the use of emulators has grown in parallel to avoid some of the difficulties presented by real devices such as variability and reliability. In this paper, we present a memristive emulator designed using a Switched Capacitor (SC), this is, an analog component/ block and a control part or block implemented using stochastic computing (SCo) and therefore fully digital. Our design is thus a mixed signal circuit. Memristor equations are implemented using stochastic computing to generate the control signals necessary to work with the controllable resistor implemented as switched capacitor.

Multiple valued logic (MVL) has proven to be a better alternative and solution to the challenges of traditional binary logic because of its fast computation, fewer interconnects, and small die. It is a potential candidate for future digital design because it allows energy-efficient, low-complex, and high-speed circuits. This paper introduces a new resistive-load two-dimensional field effect transistor-based ternary logic gates, wherein the active resistive-load is replaced with memristor to reduce chip area and power consumption. A memristor-based standard ternary inverter (STI) is designed using GNRFET, MoS2 FET, WSe2 FET, and FinFET, and their performance metric such as delay, power, and energy delay product (EDP) are analyzed. The results show that the proposed design achieves 50% reduction in circuit area, the average power dissipation is reduced by 11.7X, 6.8X, and 3.2X for GNRFET, MoS2 FET, and WSe2 FET, respectively, as compared to FinFET-based ternary inverter. Moreso, other logic gates such as OR, NOR, AND and NAND were simulated in T-SPICE EDA tool, and the results and truth table are in good agreement.

Consciousness is a special type of interaction between subjects exchanging by lingua quanta (phonemes). A set of lingua quanta composes a thesaurus placed on the edge of chaos. Its library is a memory, modification of which is due to tuning of memristive neural elements scattered in the brain volume. The memristive neural model takes into consideration two types of neurons - excitatory and inhibitory and the current leakage, all at the body temperature, T = 309 K. At such temperatures only heavy ions like hydrogen ions - protons can pass robustly through the water medium of the brain. The robust ion transport is proton water wires supported by the Grotthuss mechanism. Final aims of the ions are the gap junctions (electric synapses) linking nearest neurons. Following these observations, a model of excitable nervous tissue is constructed. Namely, a difference mapping on the basis of sigmoid curves can reproduce chaotic modes of neural activity proved by positive values of the Lyapunov exponent. The edge of chaos is placed near the bifurcation boundary dividing the chaos and the periodic convulsive activity typical at the epileptic discharges. In this region the self-sustained spiral waves occur. An intermittent activity of the competing excitatory and inhibitory neurons is observed on the edge of chaos. The intermittent electrical activity of neural tissues is demonstrated by records both from different literature issues and records made by the author together with DR. A. Dudkin on slices of CA1 field of the hippocampus.