The paper first compares the turn-off performance of two package solutions (3-lead vs 4-lead) in Super-Junction MOSFETs. It is commonly assumed that the better performance (lower switching losses) of the 4-lead is obtained thanks to the decoupling of the power and driving loop. On the contrary, in this work, the experimental results, circuit models, and Kirchhoff laws have shown that the turn-off improvement (lower turn-off losses) obtained by adopting the Kelvin source is due to the lower inductance of the driver loop in comparison with the power loop inductance, instead of the decoupling between these loops.

In the pursuit of energy-efficient spiking neural network (SNN) hardware, synaptic devices lev-eraging emerging memory technologies hold significant promise. This study investigates the ap-plication of the recently proposed HfO2/SiO2-based interface dipole modulation (IDM) memory for synaptic spike timing-dependent plasticity (STDP) learning. Firstly, through pulse measure-ments of IDM metal-oxide-semiconductor (MOS) capacitors, we demonstrate that IDM exhibits an inherently nonlinear and near-symmetric response. Secondly, we discuss the drain current re-sponse of a field-effect transistor (FET) incorporating a multi-stack IDM structure, revealing its nonlinear and asymmetric pulse response, and suggest that the degree of the asymmetry depends on the modulation current ratio. Thirdly, to emulate synaptic STDP behavior, we implement dou-ble-pulse-controlled drain current modulation of IDMFET using a simple bipolar rectangular pulse. Additionally, we propose a double-pulse-controlled synaptic depression that is valuable for optimizing STDP-based unsupervised learning. Integrating the pulse response characteristics of IDMFETs into a two-layer SNN system for synaptic weight updates, we assess training and classification performance on handwritten digits. Our results demonstrate that ID-MFET-based synaptic devices can achieve classification accuracy comparable to previously re-ported simulation-based results.

In this paper, the single event burnout(SEB) and reinforcement structure of 1200V SiC MOSFET (SG-SBD-MOSFET) with split gate and schottky barrier diode(SBD) embedded were studied. The device structure was established using Sentaurus TCAD, and the transient current changes of single event effect(SEE), SEB threshold voltage, as well as the regularity of electricfield peak distribution transfer were studied when heavy ions were incident from different regions of the device. Based on SEE analysis of new structural device, two reinforcement structure designs for SEB resistance were studied, namely the expansion of P+body contact area and the design of multi-layer N-type interval buffer layer. Firstly, two reinforcement schemes for SEB were analyzed separately, and then comprehensive design and analysis were carried out. The results showed that the SEB threshold voltage of heavy ions incident from the N+source region was increased by 16% when using the P+body contact area extension alone; When the device is reinforced with multi-layer N-type interval buffer layer alone, the SEB threshold voltage increases by 29%; The comprehensive use of P+body contact area expansion and multi-layer N-type interval buffer layer reinforcement increased the SEB threshold voltage by 33%. Overall, the breakdown voltage of the reinforced device decreased from 1632.935V to 1403.135V, which can be seen as reducing the remaining redundant voltage to 19%. The device performance was not significantly affected.

Emerging semiconductor devices often lack accurate analytical models. The same is usually true of any devices working under extreme conditions like cryogenic temperatures. The usual workaround involves the use of approximation models, usually based on lookup tables or neural networks individually fitted to measurement data. In the case of experimental devices or ones working under extreme conditions, the number of units available for measurement is limited. As a result, the number of approximation-model instances is too small to enable a statistical simulation of even middle-sized circuits, which is a necessary step in integrated-circuit design since it provides the realistic picture of the circuit’s behavior in the presence of manufacturing process variations. Approximation models using structure parameters as inputs do exist in the literature, but are only useful if the end user knows the statistical distributions of those parameters, which is not usually the case. We propose a technique based on generative machine learning, namely the variational autoencoder, that uses only a small sample of devices to capture the essential features of their I–V curves under process variations and subsequently generates an arbitrary number of similarly disturbed curves. The model trained on as few as 20 instances per device type is shown to precisely reproduce the distributions of period and power consumption of a ring oscillator.

Power converter technologies have become increasingly vital in various applications due to their efficient management of electrical energy. With the growing prominence of renewable energy sources like solar and wind, the high penetration of power electronic converters has been justified. However, ensuring power quality has emerged as a significant challenge for grid-connected power converters. The divergence from the ideal sinusoidal waveform in terms of magnitude and frequency impacts both grid-side currents and voltages. Several studies have proposed solutions to address power quality issues at the load side. The advancement of power converters has been fueled by the development of high-performance microprocessors and the emergence of high-speed switching devices, such as SiC-MOSFETs. This paper focuses on the design of voltage source converters, particularly those based on SiC-MOSFET semiconductor devices. The article presents the design of H-Bridge cells, discusses two-level voltage source converters based on cascade H-Bridge cells in parallel configuration with experimental fault analysis, addresses the seven-level voltage source converters topology, and explores the design and experimental results of the matrix converter. The findings underscore the importance of considering the entire converter design for improved performance at high switching frequencies. The article concludes by summarizing the main outcomes and implications of this research.