Disease detection and prediction have been one of the most frequent uses of machine learning models in the last decade, and Parkinson's disease is no exception. It is common for people in their old age to have one form of disease or another depending on the circumstances in which they find themselves. This study analyzed and evaluated various supervised machine learning models to detect the presence of Parkinson's disease in elderly individuals. An extreme gradient boosting model, along with other models, such as naïve Bayes, random forest, K-nearest neighbor, and support vector machine (SVM), was implemented to determine the best outcome. The extreme gradient boosting (XGBoost) model is a powerful boosting machine learning technique, particularly in terms of speed and accuracy. The results showed that the XGBoost model, which is an optimized version of the other boosting models, is capable of projecting the presence of Parkinson's disease with very high accuracy compared to other algorithms. The implemented classification algorithm extreme gradient boosting method achieved approximately 98 % accuracy, 97.5 % precision, 100.0 % recall, and 98.7% f1-score which are high compared with the results found in the existing literature.

The effectiveness of Fuzzy Inference Systems (FISs) in manipulating uncertainty and nonlinearity makes them a subject of significant interest for decision-making in embedded systems. Accordingly, optimizing FIS hardware improves its performance, efficiency, and capabilities, leading to a better user experience, increased productivity, and cost savings. To be compatible with the limited power budget in most embedded systems, this paper presents a framework to realize ultra-low power FIS hardware. It supports optimizations for both conventional arithmetic as well as MSDF-computing to be highly consistent with MSDF-based sensors. In MSDF-computing FIS all the processes of fuzzification, inference, and defuzzification are done on serially coming data bits. To demonstrate the efficiency of the proposed framework, we utilized Matlab, Chisel3, and Vivado to implement it from high-level descriptions of FIS to hardware synthesis. We also developed a Scala library in Chisel3 to establish a connection between these tools, bridging the gap, and facilitating design space exploration at the arithmetic level. Furthermore, we realized an FIS for the navigation of autonomous mobile robots in unknown environments. Synthesis results show the superiority of the output of our suggested design framework in terms of resource usage as well as power and energy consumption compared to the Matlab HDL code generator output.

Deep Neural Network (DNN) inference demands substantial computing power, resulting in significant energy consumption. A large number of negative output activations in convolution layers are rendered zero due to the invocation of the ReLU activation function. This results in a substantial number of unnecessary computations that consume significant amounts of energy. This paper presents ECHO: Energy-efficient Computation Harnessing Onilne Arithmetic - A MSDF-based accelerator for DNN inference, designed for computation pruning, utilizing an unconventional arithmetic paradigm known as online/ most-significant digit first (MSDF) arithmetic which performs computations in a digit-serial manner. The MSDF digital serial computation of online arithmetic enables overlapped computation of successive operations leading to substantial performance improvements. The online arithmetic, coupled with a negative output detection scheme, facilitates early and precise recognition of negative outputs. This, in turn, allows for the timely termination of unnecessary computations, resulting in a reduction of energy consumption. The implemented design has been realized on the Xilinx Virtex-7 VU3P FPGA and subjected to a comprehensive evaluation through a rigorous comparative analysis involving widely used performance metrics. Experimental results demonstrate promising power and throughput improvements compared to contemporary methods. In particular, the proposed design achieved an average improvement in power consumption of up to 81%, 82.9%, and 40.6% for VGG-16, ResNet-18, and ResNet-50 workloads compared to the conventional bit-serial design, respectively. Furthermore, significant average speedups of 2.39×, 2.6×, and 2.42 were observed when comparing the proposed design to conventional bit-serial designs for VGG-16, ResNet-18, and ResNet-50 models respectively.