Version 1
: Received: 8 April 2024 / Approved: 8 April 2024 / Online: 8 April 2024 (14:46:36 CEST)
How to cite:
Ibrahim, M.S.; Usman, M.; Lee, J. ECHO: Energy-Efficient Computation Harnessing Online Arithmetic – a MSDF-Based Accelerator for DNN Inference. Preprints2024, 2024040561. https://doi.org/10.20944/preprints202404.0561.v1
Ibrahim, M.S.; Usman, M.; Lee, J. ECHO: Energy-Efficient Computation Harnessing Online Arithmetic – a MSDF-Based Accelerator for DNN Inference. Preprints 2024, 2024040561. https://doi.org/10.20944/preprints202404.0561.v1
Ibrahim, M.S.; Usman, M.; Lee, J. ECHO: Energy-Efficient Computation Harnessing Online Arithmetic – a MSDF-Based Accelerator for DNN Inference. Preprints2024, 2024040561. https://doi.org/10.20944/preprints202404.0561.v1
APA Style
Ibrahim, M.S., Usman, M., & Lee, J. (2024). ECHO: Energy-Efficient Computation Harnessing Online Arithmetic – a MSDF-Based Accelerator for DNN Inference. Preprints. https://doi.org/10.20944/preprints202404.0561.v1
Chicago/Turabian Style
Ibrahim, M.S., Muhammad Usman and Jeong-A Lee. 2024 "ECHO: Energy-Efficient Computation Harnessing Online Arithmetic – a MSDF-Based Accelerator for DNN Inference" Preprints. https://doi.org/10.20944/preprints202404.0561.v1
Abstract
Deep Neural Network (DNN) inference demands substantial computing power, resulting in significant energy consumption. A large number of negative output activations in convolution layers are rendered zero due to the invocation of the ReLU activation function. This results in a substantial number of unnecessary computations that consume significant amounts of energy. This paper presents ECHO: Energy-efficient Computation Harnessing Onilne Arithmetic - A MSDF-based accelerator for DNN inference, designed for computation pruning, utilizing an unconventional arithmetic paradigm known as online/ most-significant digit first (MSDF) arithmetic which performs computations in a digit-serial manner. The MSDF digital serial computation of online arithmetic enables overlapped computation of successive operations leading to substantial performance improvements. The online arithmetic, coupled with a negative output detection scheme, facilitates early and precise recognition of negative outputs. This, in turn, allows for the timely termination of unnecessary computations, resulting in a reduction of energy consumption. The implemented design has been realized on the Xilinx Virtex-7 VU3P FPGA and subjected to a comprehensive evaluation through a rigorous comparative analysis involving widely used performance metrics. Experimental results demonstrate promising power and throughput improvements compared to contemporary methods. In particular, the proposed design achieved an average improvement in power consumption of up to 81%, 82.9%, and 40.6% for VGG-16, ResNet-18, and ResNet-50 workloads compared to the conventional bit-serial design, respectively. Furthermore, significant average speedups of 2.39×, 2.6×, and 2.42 were observed when comparing the proposed design to conventional bit-serial designs for VGG-16, ResNet-18, and ResNet-50 models respectively.
Computer Science and Mathematics, Hardware and Architecture
Copyright:
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
