A Novel FEC Implementation for VSAT Terminals Using High-Level Synthesis

1. Introduction

Hubless full-mesh very small aperture terminal (VSAT) communication systems are increasingly adopted in satellite networks for their resilience against single points of failure, support for direct VSAT-to-VSAT connectivity, and enhanced security through private network isolation  [52]. Unlike traditional star-configured VSAT architectures that rely on a central hub, hubless full-mesh systems eliminate hub dependency and enable direct remote-to-remote communication, which is critical for modern satellite applications such as broadband connectivity, IoT backhaul, and emergency communications. Reliable satellite communication requires robust forward error correction (FEC) to mitigate noisy channel conditions and maintain data integrity. Conventional FEC schemes such as turbo product codes (TPCs) [64], convolutional codes [59,61,62,63], and Reed–Solomon (RS) codes [59,60,61] have been widely deployed. However, low-density parity-check (LDPC) codes, and particularly quasi-cyclic LDPC (QC-LDPC) codes, have gained prominence due to their superior error-correction capability and hardware efficiency. QC-LDPC codes exploit structural regularity in the parity-check matrix, reducing memory and interconnect complexity while achieving near-optimal performance [50]. These advantages have led to their adoption in modern standards such as DVB-S2 [59], IEEE 802.11n (WiFi) [55], and 5G NR [58]. The sum-product (SP) algorithm, also known as belief propagation (BP), remains the performance benchmark for LDPC decoding [3], but its probability-domain arithmetic is computationally expensive for resource-constrained FPGAs. Simplified variants such as min-sum (MS) [2,35] and normalized min-sum (NMS) reduce complexity by replacing multiplications with add-compare-select operations, albeit at the cost of some coding gain. Further refinements, including second-minimum approximation (SAMS) [7], two-dimensional MS (2D-MS) [32], and two-dimensional normalized min-sum (2D-NMS) [30], improve accuracy with modest overhead. Traditional register-transfer-level (RTL)-based implementations of LDPC decoders are time-consuming, error-prone, and difficult to scale across evolving FPGA platforms. High-Level Synthesis (HLS) offers a modern design methodology that accelerates development, improves portability, and enables rapid design-space exploration without sacrificing hardware efficiency. For FPGA targets such as VSATPlus^®, decoder microarchitecture strongly impacts throughput, latency, and power. Fully parallel layered designs achieve high per-iteration throughput but incur dense interconnect and tight timing closure [36]. Partially parallel designs reduce wiring and power at the cost of lower throughput [37], while pipelined block-serial decoders minimize area but increase latency [38]. Scheduling also influences convergence and memory organization: flooding requires more iterations and higher energy, whereas layered scheduling reduces iterations but demands careful memory banking [10,11]. Despite these advances, existing FPGA implementations struggle to balance error-correction performance, resource utilization, and power efficiency under stringent constraints typical of satellite systems. This gap motivates the need for an approach that combines algorithmic improvements with a scalable, hardware-aware design methodology leveraging HLS. To address this challenge, this work proposes a layered 2D-Corrected Normalized Min-Sum (2D-CNMS) decoder integrated into an HLS-based design flow for generating reusable LDPC IP cores. The proposed architecture incorporates dyadic, multiplier-free normalization and dual-scaling of the first and second minima, achieving near-BP performance while minimizing resource usage and power consumption.

The main contributions of this paper are as follows: (1) A hardware-aware LDPC decoder architecture based on the 2D-CNMS algorithm optimized for FPGA implementation; (2) An HLS-based design flow for generating reusable LDPC IP cores, reducing development complexity compared to traditional RTL approaches; (3) Comprehensive evaluation of post-implementation error-correction performance, resource utilization, and throughput under realistic satellite channel conditions. The remainder of this paper is organized as follows: Section 2 describes the VSATPlus^® system and its architectural constraints. Section 3 and Section 4 present the proposed LDPC decoder and algorithmic enhancements. Section 5 details the FPGA-oriented architecture. Section 7 reports simulation results and analyzes complexity-performance trade-offs. Finally, Section 8 concludes the paper and outlines future research directions.

2. VSATPlus System Overview

The VSATPlus [66] system provides full-mesh, single-hop connectivity within a satellite network, leveraging multi-frequency time division multiple access (MF-TDMA) technology. Each terminal buffers user data and transmits it in short, high-speed bursts scheduled to avoid overlap, ensuring efficient satellite resource utilization without requiring a central hub for scheduling. This hubless architecture supports diverse satellite applications, including broadband connectivity, IoT backhaul, emergency communications, and enterprise networking, where reliability and scalability are critical. Figure 1 illustrates one example of VSATPlus deployment in air traffic control (ATC), showing direct IP connectivity between area control centers (ACCs) and airports across regions. Similar principles apply to other mission-critical satellite services requiring secure, low-latency communication.

The VSATPlus modem is highly agile, capable of varying multiple parameters burst-by-burst. This flexibility enables carrier-to-carrier hopping for both transmit and receive over 32 carriers, along with adaptive modulation and FEC changes. This capability, referred to as Mesh-ACM^TM, dynamically adjusts modulation and coding to accommodate different terminal antenna sizes and varying channel conditions across the network, optimizing throughput and reliability [53]. Figure 2 shows the architecture of a VSATPlus full-mesh, hubless network employing Ku-band and C-band satellite links for high-throughput communication. The satellite facilitates signal transmission from ground stations operating on both frequency bands, enabling simultaneous multi-band connectivity.

The network consists of six nodes ($A_1$ to $A_6$), interconnected in a full-mesh topology to ensure direct, bidirectional communication between all nodes. This architecture demonstrates the robustness and scalability of VSATPlus for distributed satellite applications beyond ATC, including broadband and enterprise networking.

3. Decoding Algorithmic Principles

QC-LDPC codes apply parity-check matrices tiled by $Z\times Z$ submatrices that are either circulant permutations of the identity or zeros [29]. This regular structure yields compact representations and lower memory requirements while enabling highly parallel, hardware-efficient decoders—an attractive performance/complexity trade-off for high-throughput satellite links. In satellite communication systems, where long propagation delays and limited link budgets make re-transmissions costly, efficient LDPC decoding is essential to maintain reliability and throughput. Although QC-LDPC codes may be degree-irregular (row and column weights $(d_c,d_v)$ can vary), the locations of ones in H are deterministically specified by the permutation matrix and its circulant shifts, producing predictable, conflict-free access patterns rather than random placement [17]. Furthermore, the QC form organizes H as a regular array of blocks, with Z distinct memory banks for variable node (VN) data, enabling blockwise schedules that achieve scalable parallelism. A compressed permutation matrix, illustrated in Table 1, stores only shift offsets, where dash marks a zero block and non-negative entries specify the cyclic shift of the identity, minimizing footprint and simplifying decoder configuration. Owing to these advantages, QC-LDPC codes are widely adopted in modern communication standards.

The decoding of QC-LDPC codes typically employs BP algorithms, which are broadly classified based on the nature of the message information exchanged during iterations. Hard-decision decoders, such as the bit-flipping (BF) algorithm, operate on binary decisions extracted directly from the channel [39]. Conversely, soft-decision decoding techniques, including the sum-product (SP) algorithm and its computationally simplified variant, the min-sum (MS) algorithm, leverage soft information in the form of log-likelihood ratios (LLRs) [26,68]. These iterative message-passing algorithms exchange extrinsic information between variable nodes (VNs) and check nodes (CNs) over a bipartite graph representation of the parity-check matrix H, known as a Tanner graph [27]. This graph-based framework underpins the inference mechanism that progressively refines the reliability of decoded bits with each iteration.

The structure of the LDPC parity-check matrix H used in this work is derived from the IEEE 802.16e (WiMAX) standard. The matrix is constructed from a permutation matrix, shown in Table 1, composed of integer shift values and null entries, expanded by a lifting factor Z. The resulting H matrix is sparse and quasi-cyclic as illustrated in Figure 3. Each diagonal or off-diagonal band in the figure corresponds to a circulant permutation matrix. Their distribution reflects the structured connectivity of VNs (columns) and CNs (rows).

3.1. Sum-Product / Belief Propagation

The SP decoding algorithm, also known as the BP [30], initiates by calculating the LLRs for each received channel symbol $r_i$ at time i under an AWGN channel model, as follows:

$$LL{R}_i=log{\displaystyle \frac{Pr\left(r_i\right|t_i=1)}{Pr\left(r_i\right|t_i=-1)}}={\displaystyle \frac{2r_i}{{\sigma }^2/2}}$$

(1)

where ${\sigma }^2$ is the channel noise power following the Gaussian distribution. Initially, messages passed from variable node v to the connected check node c are set to the LLR value derived from the received symbol, as given by:

$$L_{v\to c}=\sum _{c^{\prime }\in \mathcal{M}\left(v\right)\setminus c}{L}_{c^{\prime }\to v}$$

(2)

where $c^{\prime }\in \mathcal{M}\left(v\right)\setminus c$ represents the set of check nodes connected to the variable node v, excluding c. Next, the check node information is updated as follows:

$$L_{c\to v}^{(\ell )}=2{tanh}^{-1}(\prod _{v^{\prime }\in \mathcal{N}\left(c\right)\setminus v}tanh{\displaystyle \frac{L_{v^{\prime }\to c}^{(\ell -1)}}{2}})$$

(3)

Once the convergence condition is satisfied or the maximum number of iterations is reached, the operation terminates. Subsequently, the hard decision for each variable node, v, is computed based on its LLR:

$$L_v=LLR+\sum _{c^{\prime }\in \mathcal{M}\left(v\right)}{L}_{c^{\prime }\to v}$$

(4)

If $L_v\ge 0$, then the estimated transmitted bit value is 0, otherwise it is considered as 1.

3.2. Min-Sum

While BP achieves excellent error-correction performance, its reliance on nonlinear functions and probability-domain operations results in high computational complexity, motivating the development of simplified algorithms such as Min-Sum. The MS decoding algorithm simplifies the computational complexity of the BP algorithm by replacing nonlinear hyperbolic tangent functions with a minimum operation. Thus, the check node update equation simplifies to:

$$L_{c\to v}^{(\ell )}=\left(\prod _{v^{\prime }\in \mathcal{N}\left(c\right)\setminus v}\mathrm{sign}\left(L_{v^{\prime }\to c}^{(\ell -1)}\right)\right)\underset{v^{\prime }\in \mathcal{N}\left(c\right)\setminus v}{min}\left|L_{v^{\prime }\to c}^{(\ell -1)}\right|$$

(5)

The variable nodes update and hard decision processes remain consistent with the BP algorithm.

3.3. Normalized Min-Sum

Although the MS significantly reduces hardware resource requirements and processing latency compared to the BP algorithm, it experiences degradation in BER performance, typically around $0.5-1$ dB [39]. This degradation primarily results from overestimation in extrinsic information exchange between nodes. To mitigate this effect, normalized min-sum (NMS) applies scaling factor, $\beta \in (0,1)$, to correct extrinsic information estimates, thereby enhancing practical decoding performance [24]:

$$L_{c\to v}^{(\ell )}=\left(\prod _{v^{\prime }\in \mathcal{N}\left(c\right)\setminus v}\mathrm{sign}\left(L_{v^{\prime }\to c}^{(\ell -1)}\right)\right)\beta \underset{v^{\prime }\in \mathcal{N}\left(c\right)\setminus v}{min}\left|L_{v^{\prime }\to c}^{(\ell -1)}\right|$$

(6)

Whereas NMS attenuates the check-node minima by multiplying the raw minimum magnitude by a constant $0<\beta <1$, offset min-sum (OMS) instead applies a fixed subtraction to correct for the systematic over-estimation introduced by the plain min-sum rule [25]. In OMS, each check-to-variable message is computed as:

$$L_{c\to v}^{(\ell )}=\left(\prod _{v^{\prime }\in \mathcal{N}\left(c\right)\setminus v}\mathrm{sign}\left(L_{v^{\prime }\to c}^{(\ell -1)}\right)\right)max\left[\left(\underset{v^{\prime }\in \mathcal{N}\left(c\right)\setminus v}{min}\left|L_{v^{\prime }\to c}^{(\ell -1)}\right|\right)-\eta ,0\right]$$

(7)

where $\eta >0$ is the offset parameter chosen to minimize the performance loss relative to the full belief-propagation algorithm [25]. Because the offset operation requires only a single subtraction per edge rather than a multiplication, OMS offers reduced critical-path latency and lower hardware resource usage compared to NMS.

3.4. 2-Dimensional Normalized Min-Sum

In the standard NMS algorithm, a single constant scaling factor compensates the overestimated magnitudes of all incoming check-to-variable messages. However, the extrinsic magnitude sent to a VN equals the smallest incoming magnitude, ${min}_1$, for all edges except the argmin edge, which uses the second-smallest incoming magnitude, ${min}_2$, due to edge exclusion. Consequently, applying one scale for both cases can miscalibrate some messages and degrade performance. The 2D-NMS addresses this by applying distinct scaling (${\beta }_1,{\beta }_2$), conditioned on whether ${min}_1$ or ${min}_2$ is used, yielding more accurate LLRs with only modest added complexity [31]:

$$L_{c\to v}^{(\ell )}=\left(\prod _{v^{\prime }\in \mathcal{N}\left(c\right)\setminus v}\mathrm{sign}\left(L_{v^{\prime }\to c}^{(\ell -1)}\right)\right)\times \left\{\begin{array}{c}{\beta }_2·\underset{2}{min}\hfill \\ {\beta }_1·\underset{1}{min}\hfill \end{array}\right.$$

(8)

For LDPC decoders employing the 2D-NMS algorithm, the optimal normalization factors (${\beta }_1,{\beta }_2$), are predominantly determined by the check node degree ($d_c$), which is determined by the parity check matrix.

3.5. 2-Dimensional Min-Sum

While 2D-NMS compensates the check-node magnitude bias via the scaling pair (${\beta }_1,{\beta }_2$), it applies the same gain to both message flows. Density-evolution analysis in [32] shows that the residual bias on the variable-to-check stream differs statistically from that on the check-to-variable stream. Therefore, introducing a second, direction-specific scaling pair eliminates this asymmetry and closes the remaining gap to SP decoding with only two extra multiplications per edge. To address this residual asymmetry more effectively, [32] proposes applying iteration-dependent scale factors (${\alpha }^{(\ell )},{\beta }^{(\ell )}$) directly to the extrinsic LLRs on each edge, resulting in:

$${\tilde{L}}_{v\to c}^{(\ell )}={\alpha }^{(\ell )}{L}_{v\to c}^{(\ell )}$$

(9)

While the corresponding check-to-variable updates is as follows:

$${\tilde{L}}_{c\to v}^{(\ell )}=\left(\prod _{v^{\prime }\in \mathcal{N}\left(c\right)\setminus v}\mathrm{sign}\left({\tilde{L}}_{v^{\prime }\to c}^{(\ell -1)}\right)\right){\beta }^{(\ell )}\underset{v^{\prime }\in \mathcal{N}\left(c\right)\setminus v}{min}\left|{\tilde{L}}_{v^{\prime }\to c}^{(\ell -1)}\right|$$

(10)

Although (${\alpha }^{(\ell )},{\beta }^{(\ell )}$) can be optimized adaptively based on the code structure and channel SNR, [32] demonstrates that exhaustive AWGN profiling across the operational $E_b/N_0$ range yields two fixed scale factors that preserve virtually all of the SP decoder’s extrinsic-information fidelity.

4. 2-Dimensional Corrected Normalized Min-Sum

For VSATPlus terminals, even modest coding-gain improvements translate into reduced power-amplifier back-off and increased fade margins. However, the SP decoding algorithm remains computationally impractical for the throughput and power envelopes of the target FPGA platforms. Building on [31,32], we propose a two-dimensional corrected normalized min–sum (2D-CNMS) decoder that preserves the add–compare–select arithmetic of MS while recovering a substantial fraction of the residual gap to SP algorithm. The update introduces two shift-based per-edge scalings per iteration and incurs no additional on-chip memory, thereby maintaining low architectural complexity. Therefore, the scaled variable-to-check update is defined as:

$${\tilde{L}}_{v\to c}^{(\ell )}=\overline{\alpha }{L}_{v\to c}^{(\ell )}$$

(11)

While, the scaled check-to-variable update is given by:

$${\tilde{L}}_{c\to v}^{(\ell )}=\left(\prod _{v^{\prime }\in \mathcal{N}\left(c\right)\setminus v}\mathrm{sign}\left({\tilde{L}}_{v^{\prime }\to c}^{(\ell -1)}\right)\right)\times \left\{\begin{array}{c}\overline{{\beta }_2}·\underset{2}{min}\hfill \\ \overline{{\beta }_1}·\underset{1}{min}\hfill \end{array}\right.$$

(12)

Similar to 2D-NMS algorithm, ${min}_1$ and ${min}_2$ denote the smallest and second-smallest absolute values of the incoming messages $|{\tilde{L}}_{v^{\prime }\to c}^{(\ell -1)}|$, where $v^{\prime }\in \mathcal{N}\left(c\right)\setminus v$.

5. 2D-CNMS Hardware Implementation

Hand-optimized RTL design has traditionally been the standard approach for FPGA-based LDPC decoders. However, High-Level Synthesis (HLS) methodologies [16] and commercial toolchains such as Vivado HLS [67] now offer a more productive alternative by enabling designers to specify the decoder in C/C++ or SystemC and automatically generate synthesizable RTL. In practice, HLS significantly reduces design and verification effort [15], while achieving area, timing, and power results comparable to expert-tuned HDL implementations [15]. Furthermore, a single high-level source is portable across FPGA families and integrates seamlessly with the VSATPlus C-based simulation environment, facilitating rapid design-space exploration and system-level validation. Algorithm 1 summarizes the layered scheduling strategy employed in the proposed 2D-CNMS decoder. Compared to conventional layered MS, the proposed approach introduces a uniform variable-to-check scaling factor, $\overline{\alpha }$, and a two-level check-to-variable scaling pair (${\overline{\beta }}_1,{\overline{\beta }}_2$), conditioned on whether the outgoing message is derived from ${min}_1$ or ${min}_2$. These refinements improve extrinsic information accuracy while preserving the low-complexity arithmetic of MS.

The proposed decoder is implemented using Vivado HLS 2024, leveraging loop-level parallelism and pipelining to maximize throughput. Inner loops responsible for CN and VN updates are partially or fully unrolled to generate multiple CN→VN and VN→CN messages per cycle, while outer loops are pipelined to minimize the initiation interval (II), enabling iteration overlap and reducing latency. The inherent layered structure of QC-LDPC codes facilitates deterministic memory banking and partitioning across Z dual-port block RAMs (BRAMs), supporting concurrent read–modify–write operations aligned with layer boundaries. Address generation is performed using two ROM-based lookup tables (LUTs) precomputed from the base matrix: $\mathcal{N}\left(c\right)$ for CN updates and $\mathcal{M}\left(v\right)$ for VN updates. These index tables enable constant-time routing without additional buffering or pointer chasing, ensuring efficient memory access.

The HLS-based 2D-CNMS decoder architecture, illustrated in Figure 4, comprises two fully parallel processing engines: one dedicated to CN message computation and the other to VN message computation. Each engine interfaces directly with dual-port BRAM banks under the control of a compact ROM storing non-negative cyclic-shift offsets and connection degrees derived from the base matrix.

In the CN engine, which comprises $M/Z$ parallel pipelines, each pipeline retrieves a Z-wide vector of extrinsic LLRs from the VN RAM, applies a fixed-depth tree of four-input comparators to identify the smallest and second-smallest magnitudes, determines the overall output sign through a single XOR reduction stage, and adjusts these minima using normalization factors (${\overline{\beta }}_1,{\overline{\beta }}_2$). The normalized extrinsic messages are then written back to the CN-RAM via the dual-port interface. Similarly, the VN engine, consisting of $N/Z$ parallel pipelines, reads the updated CN messages along with the original channel LLRs, accumulates them using an adder tree, subtracts each corresponding extrinsic to form new messages, scales the result by $\overline{\alpha }$, applies eight-bit saturation, and generates provisional hard decisions based on the sign. Both the updated soft-value vectors and hard-decision bits are subsequently written to the VN RAM and output RAM, respectively.

6. End-to-End Vivado Block Design

Figure 5 illustrates the integrated encoder–channel–decoder chain instantiated in Vivado by introducing external IP cores implemented using Vitis HLS 2024. Although the LDPC IP core was validated at a clock frequency of 400 MHz, the design employs a 100 MHz system clock generated by the Clocking Wizard IP and distributed via the Processor System Reset module. Each frame begins with a single-cycle start pulse, and all AXI4-Stream interfaces operate without backpressure, with the ready signal held asserted.

A pseudorandom source generates independent and identically distributed (i.i.d.) Bernoulli bits using a linear feedback shift register (LFSR) method. After AXI4-Stream handshakes, the QC-LDPC encoder accepts the payload and emits a serialized codeword. An RTL binary phase-shift keying (BPSK) modulator maps bits to signed 8-bit symbols with values $\{+127,-128\}$. Additive noise is produced by an external AWGN IP implementing the Box–Muller transform (see Appendix B). Variance and seed registers are programmed via AXI4-Lite memory-mapped writes issued by the Zynq UltraScale+ processing system (PS), enabling deterministic initialization and run-time reconfiguration of the programmable logic (PL) core. The noise stream is buffered in a FIFO to decouple producer and consumer timing. On readout, the noise is added to the BPSK waveform, saturated to $[-128,127]$, and treated as the input LLR stream for the decoder. Similar to AWGN parameters, the iteration limit, ${\mathrm{Itr}}_{max}$, is also configured by a control register for each frame.

During transmission, the reference bit for each payload position is stored in a reference FIFO. In parallel, a channel hard decision is derived from the sign of the saturated received sample and stored in a second FIFO to measure uncoded performance. When decoded bits become available, they are compared against the reference FIFO to accumulate the post-decoder error count, while the channel-hard stream is compared against the same reference to count bit flips caused by noise.

7. Emulation Results

We evaluate decoding algorithms under a layered schedule on the QC-LDPC code $(1056,704)$ with ${\mathrm{Itr}}_{max}=50$ using 8-bit fixed-point LLRs (clip/saturate) and syndrome-based early termination. The channel is AWGN and $E_b/N_0$ is swept on a uniform grid with sufficient frames per point to probe down to $\mathrm{BER}\le {10}^{-8}$. All baselines use identical quantization, stopping criteria, and layered scheduling for a fair comparison. Unlike conventional NMS, the proposed 2D-CNMS introduces dual-direction scaling and normalization refinements that significantly improve convergence speed and error-floor performance while maintaining FPGA-friendly complexity.

According to [31], the optimal two-level CN normalization factors $({\beta }_1,{\beta }_2)$ decrease with increasing check-node degree ($d_c$) and approach constants at high SNR. Specifically, for the regular codes with $d_c=6$ and $\mathrm{SNR}\in [0,4]$ dB, ${\beta }_1\in [0.50,0.90]$ and ${\beta }_2\in [0.27,0.50]$, trending toward the upper end as SNR rises. Consistently, [32] reports nearly iteration-invariant scalings for IEEE 802.11n $(1944,1296)$, $R=2/3$ as $\overline{\alpha }\approx 0.9007$ and $\overline{\beta }\approx 0.8973$, achieving BER within $0.02$ dB of SP algorithm over $E_b/N_0\in [1.4,2.6]$ dB. In line with [1], the strongest single-scalar NMS baseline uses a fixed normalization schedule:

$${\beta }^{(\ell )}=3/4+2^{-(\ell +1)}\mathrm{if}2\le \ell \le 5,\mathrm{else}3/4$$

(13)

where ℓ represents the number of iterations.

These observations support fixed, iteration-invariant gains. Guided by coarse-to-fine emulation sweeps on the target IEEE 802.16e QC-LDPC codes (rates $1/2,2/3,3/4$), we therefore map $({\beta }_1,{\beta }_2)$ to $\overline{{\beta }_1}=0.8125$ and $\overline{{\beta }_2}=0.875$, and set the VN gain to $\overline{\alpha }=0.75$. All scalings are implemented via shift-and-subtract to eliminate multipliers and extra memory.

7.1. Performance and Complexity Comparison

Figure 6 compares full-BP, layered-BP, NMS ($\beta =0.75$) [1,24], 2D-MS ($\overline{\alpha }=\overline{\beta }\approx 0.899$) [39], 2D-NMS (${\beta }_1,{\beta }_2$)$=$($0.75,0.875$) [31], and the proposed 2D-CNMS ($\overline{\alpha },\overline{{\beta }_1},\overline{{\beta }_2}$)$=$($0.75,0.8125,0.875$) on QC-LDPC code ($1056,704$) with ${\mathrm{Itr}}_{max}=50$. Across the operational $E_b/N_0$ range, 2D-CNMS closely follows layered-BP and consistently outperforms NMS, 2D-NMS, and 2D-MS. While NMS and 2D-CNMS are comparable in the waterfall region, 2D-CNMS exhibits a lower error floor in the high-SNR, outperforming even the layered-BP reference. While BP remains the theoretical benchmark, its computational complexity makes FPGA implementation impractical. 2D-CNMS achieves near-BP performance without multipliers or dividers, making it suitable for real-time FPGA deployment.

Figure 7 reports BER versus decoder iterations for the $(1056,704)$ code under BPSK/AWGN. At SNR$=2.0$ dB, the proposed 2D-CNMS achieves BER$\le {10}^{-7}$ by approximately 12 iterations, whereas the conventional NMS (with $\beta =0.75$) requires roughly 15 iterations. For SNR$\le 1.5$ dB, neither method reaches ${10}^{-7}$ within 50 iterations. Nevertheless, 2D-CNMS maintains a uniformly lower BER for the same iteration budget and, at SNR$=1.5$ dB, attains BER$\approx {10}^{-6}$ in the mid–30s iterations while NMS does not achieve ${10}^{-6}$ within 50 iterations. These iteration savings translate directly to reduced latency and higher throughput (see Section 7.3).

Figure 8 presents the $\mathrm{BER}$ performance of the proposed 2D-CNMS across $\mathrm{IEEE}802.16\mathrm{e}$ QC-LDPC code profiles. In contrast to the $\mathrm{MATLAB}$ layered-BP reference in Figure 6, the 2D-CNMS maintain a sustained waterfall region with no observable error floor over the simulated range, reaching $\mathrm{BER}<{10}^{-8}$.

Table 2 contrasts the arithmetic requirements of SP, MS, NMS, OMS, 2D-MS, 2D-NMS, and the proposed 2D-CNMS on a per-check-node basis. SP demands $d_c$ multiplications and $d_c-1$ divisions. 2D-MS retains 2 multipliers. 2D-CNMS removes multipliers and dividers and keeps the comparator count $d_c+{log}_2{d}_c-2$. Normalization is implemented by 3 subtractions and 12 bit-shifts. The resulting data path is DSP-free and FPGA-native while recovering near-SP message fidelity. In effect, 2D-CNMS trades multiplications/divisions for lightweight comparisons and shifts.

7.2. Resource Utilization

Table 3 benchmarks layered 2D-CNMS against representative HLS and hand-tuned FPGA decoders for WiMAX, Wi-Fi, and DVB-S2 standards under a uniform 100 MHz target and a fixed optimized iteration. The proposed instances deliver 29-41 Mbps coded-bit throughput with 0 DSP usage and moderate memory footprints near 97-217 BRAM-18K.

Considering (15), throughput scales approximately linearly with the clock for fixed initiation interval and bandwidth, selecting a higher target clock in Vitis HLS (which packages the blocks as Vivado IP) proportionally increases system throughput. Retargeting the same design to $f_{\mathrm{clk}}=400$ MHz with $\mathrm{II}=1$ yields a $\times 4$ speedup. A comparator–adder–shift data path plus a layered schedule provides a predictable cost–throughput operating point without multiplier-based scaling. The IEEE 802.16e permutation-matrix geometries are $12\times 24$ for rate $1/2$, $8\times 24$ for rate $2/3$, and $16\times 48$ for rate $3/4$. These geometries directly set storage depth and intra-layer parallelism for each instance.

Table 4 summarizes post-synthesis utilization and timing across multiple N, K settings and code rates. All designs remain DSP-free. LUT and FF counts stay modest in the ranges $8.7$ k-$22.9$ k and $2.6$ k-$7.5$ k. BRAM demand scales with the permutation geometry up to 217 at rate $3/4$. Measured decoding latency follows the analytic model ${\Lambda }_N$ in (14), with per-iteration costs $C_{\mathrm{iter}}$ that match the scheduled kernels. Achieved coded-bit throughput at 100 MHz spans 29-41 Mbps. These results confirm that the HLS formulation compiles to efficient RTL with stable timing and predictable scaling, while preserving the algorithmic benefits of two-dimensional dyadic normalization.

7.3. Decoding Latency Analysis

Decoding latency is measured in clock cycles to process one full codeword. Under non-overlapped AXI4-Stream I/O the total latency equals sequential input of all channel LLRs, sequential output of the final hard decisions, a fixed I/O and pipeline overhead, and an iteration-dependent compute term. For code rate $2/3$ defined by an $8\times 24$ permutation matrix, see Table 1, the lifting size is $Z=N/24$ and the information length is $K=2/3\times N$. Calibrated to the HLS schedule the per-iteration compute cost scales approximately linearly with Z. For a run with ${\mathrm{Itr}}_{max}$ decoding iterations the latency in cycles is:

$${\Lambda }_N=N+K+{\delta }_{\mathrm{pipe}}+It{r}_{max}\times C_{\mathrm{iter}}\left(Z\right)$$

(14)

with ${\delta }_{\mathrm{pipe}}$ the fixed pipeline and I/O overhead and $C_{\mathrm{iter}}\left(Z\right)$ the scheduled check-node and variable-node kernel cost per iteration. From HLS reports, as addressed in Table 4, at rate $2/3$ we conservatively upper-bound ${\delta }_{\mathrm{pipe}}=10$ cycles, $C_{\mathrm{iter}}\left(22\right)=65$ cycles for QC-LDPC ($528,352$), and $C_{\mathrm{iter}}\left(44\right)=100$ cycles for ($1056,704$).

Given a clock frequency $F_{clk}$ in $\mathrm{MHz}$ the coded-bit throughput in $\mathrm{Mbps}$ is:

$$\mathcal{T}={\displaystyle \frac{N\times F_{clk}}{\Lambda }}Mbps$$

(15)

while the information-bit throughput equals $R\times \mathcal{T}$.

Figure 9 shows RTL simulation traces via Xilinx Vivado 2024. The left cursor aligns to the first valid AXI4-Stream LLR beat and the right cursor to the last valid hard-decision beat. The signal dec_count ramps over N samples during input, the decoder executes ${\mathrm{Itr}}_{max}=32$ iterations, and the design streams out K bits. A bounded fill and drain overhead is visible in the AXI handshakes and is consistent with ${\delta }_{\mathrm{pipe}}\le 10$ cycles.

Equation (14) gives ${\Lambda }_{528}=2970$ cycles and ${\Lambda }_{1056}=4970$ cycles while Vivado reports 2037 cycles and 4876 cycles, respectively. The RTL values lie within the analytic bound and are shorter due to scheduler conservatism and the absence of backpressure.

8. Conclusion

This work presented an end-to-end FPGA implementation of a QC-LDPC decoder for VSATPlus systems using Vitis HLS and Vivado 2024. The primary contribution lies in demonstrating a practical design methodology for mapping advanced LDPC decoding techniques onto FPGA hardware through HLS-driven flows, enabling rapid prototyping and deployment without manual RTL development. The proposed architecture employs shift-and-subtract operations to eliminate multipliers and dividers, resulting in a DSP-free design optimized for resource-constrained satellite terminals.

The complete system integration was achieved using HLS-generated IP cores for the encoder, AWGN channel, and decoder. Under a 100 MHz and 400 MHz clock, the design achieves a coded-bit throughput of 29–41 Mbps and 116–164 Mbps, respectively, with moderate memory usage. Post-implementation Vivado power analysis reports an estimated dynamic power of 116 mW at 100 MHz for the encoder and 1.948 W at 400 MHz for the decoder, confirming suitability for low-power VSAT platforms. These values are consistent with reported figures for FPGA-based LDPC decoders of comparable block size (2064 bits) and code rates (1/2, 2/3, and 3/4) in the literature, where dynamic power typically ranges between 1.5 W and 3 W for high-throughput designs operating at 300–500 MHz. Fixed scaling factors were selected through empirical optimization to balance BER performance and hardware simplicity, avoiding the complexity overhead of adaptive scaling with negligible performance penalty.

Performance evaluation under AWGN, which is appropriate for GEO VSATPlus links with negligible Doppler and stable fading, shows near-BP decoding performance and no observable error floor down to $\mathrm{BER}<{10}^{-8}$. Compared to MS-family baselines, the implemented design achieves faster convergence and lower iteration counts, translating into reduced latency and higher throughput.

Future work will extend this HLS-based methodology to adaptive coding and modulation (ACM) and AI-assisted decoding for non-Gaussian channels, while incorporating detailed power and thermal profiling under realistic traffic conditions. These directions aim to further validate the practicality of HLS-driven FPGA deployment for next-generation satellite communication systems.

Appendix A.1. VSATPlus Encoder Algorithm

The VSATPlus QC-LDPC encoder leverages the Direct Encoding Method II as specified in the IEEE C802.16e-04/373r1 standard [65]. This approach is grounded in a structured matrix-partitioning technique that facilitates deterministic, low-complexity encoding suitable for hardware implementation. As illustrated in Figure A1, the parity-check matrix H is decomposed into six submatrices: $A_{(N_p-g)\times N_k}$, $B_{(N_p-g)\times g}$, $C_{g\times N_k}$, $D_{g\times g}$, $E_{g\times (N_p-g)}$, and $T_{(N_p-g)\times (N_p-g)}$, with T being a lower-triangular matrix characterized by ones along its main diagonal.

Figure A1. Structure of the QC-LDPC parity-check matrix implemented for VSATPlus based on $\mathrm{IEEE}802.16\mathrm{e}$ [65].

Figure A1. Structure of the QC-LDPC parity-check matrix implemented for VSATPlus based on $\mathrm{IEEE}802.16\mathrm{e}$ [65].

In the QC-LDPC selected for implementation and evaluation in this work, the instantiated parameters $(N_p,N_k,g)$ are: $(12,12,1)$, $(8,16,1)$, and $(12,36,1)$ for $R=1/2,2/3,3/4$, respectively, where $N_p$ and $N_k$ denote the permutation-matrix rows and columns with lifting factor $Z=N/(N_k+N_p)$. The instantiate block lengths in our experiments are $\{528,1056,2064\}$ with the three code rates.

Given a systematic input vector u, the encoding procedure begins with the computation of intermediate products $A{u}^T$ and $C{u}^T$, followed by the application of the inverse transform $T^{-1}\left(A{u}^T\right)$. The first set of parity bits, denoted $p_1$, is then computed according to:

$$p_1^T=C{u}^T+E^T{T}^{-1}\left(A{u}^T\right),$$

(A1)

which incorporates contributions from both the C and E matrices. Subsequently, the second set of parity bits, $p_2$, is obtained using:

$$p_2^T=T^{-1}(A{u}^T+B{p}_1^T),$$

(A2)

where the input u and partial parity $p_1$ are jointly encoded via the lower-triangular transformation. A high-level depiction of this block-wise encoding flow is provided in Figure A2.

Figure A2. Block diagram of the $\mathrm{IEEE}802.16\mathrm{e}$ QC-LDPC encoder architecture [65].

Figure A2. Block diagram of the $\mathrm{IEEE}802.16\mathrm{e}$ QC-LDPC encoder architecture [65].

The matrix sparsity and hierarchical decomposition yield a high-throughput, pipelined encoder design with minimal logic complexity. For a detailed derivation and theoretical justification of (A1) and (A2), refer to [65].

Appendix A.2. FPGA Implementation of VSATPlus Encoder

The QC-LDPC encoder is implemented using Vitis HLS and synthesized for the Xilinx Zynq UltraScale+ device with a target system clock of 100 MHz. The implementation leverages extensive high level synthesis optimizations including loop pipelining, aggressive unrolling, and complete array partitioning. These transformations enable deep parallelism across matrix-vector computations and circular shift operations, particularly within encoding stages. A detailed summary of the post-RTL optimized resource utilization, latency, and throughput for the specific QC-LDPC codes is presented in Table A1.

Table A1. QC-LDPC Enecoder Resource Utilization.

Table A1. QC-LDPC Enecoder Resource Utilization.

Figure A4 illustrates RTL simulation traces of the QC-LDPC encoder at $F_{clk}=100$ MHz in Vivado 2024. The left cursor is aligned to the first valid AXI4-Stream input beat, and the right cursor to the last valid output beat on the codeword port. Two counters ramps over the $K=704$ accepted information bits, and the $N=1056$ emitted code bits. The output path exhibits no backpressure and only a bounded fill/drain overhead is visible in the handshakes. The measured span between cursors is 1787 cycles at 100 MHz which is aligned with the Vitis HLS report provided in Table A1.

The simulation also verify the Gaussian noise source used for downstream link tests.

Figure A3. 12-bit LFSR with 1-bit output used in the Box-Muller method to generate i.i.d. random variable.

Figure A3. 12-bit LFSR with 1-bit output used in the Box-Muller method to generate i.i.d. random variable.

Figure A4. Encoder latency analysis of QC-LDPC $(1056,704)$ with $F_{clk}=100$ MHz via Xilinx Vivado 2024.

Figure A4. Encoder latency analysis of QC-LDPC $(1056,704)$ with $F_{clk}=100$ MHz via Xilinx Vivado 2024.