Bidirectional Reusable Subcircuit Modeling and Hierarchical Synthesis of Analog/RF Circuits with ANNs

1. Introduction

Although the concept of automated circuit sizing emerged decades ago, it continues to advance as research builds progressively on earlier developments to address increasingly complex design challenges. Over time, researchers have sought to enhance effectiveness without sacrificing efficiency, and recent advances in computer science have significantly expanded the scope of automation. With the availability of powerful computational resources and intelligent algorithms, most analog/RF sub-blocks can now be synthesized efficiently, even under stringent constraints. However, the automatic design of more complicated systems remains inefficient due to the need for a comprehensive scan of the entire design space with expensive simulations. Early approaches to automatic synthesis often relied on human expertise to establish accurate analytical models of the circuit. Different topology selection mechanisms have been used as the initial step in designing basic operational amplifier structures for given specifications. After the selection, amplifiers have been sized via an equation-based optimization tool [1,2,3,4]. Besides these initiation steps, finding the optimal solution and expanding the search space were the main considerations. Equation-based optimization tools introduced in [5,6] exploit the search capability of the genetic algorithm [7]. On the other hand, OPTIMAN [8] utilizes simulated annealing (SA) [9] to avoid getting stuck at the local optimum. In order to make automation more effective, the circuit simulator SPICE has been first incorporated into the synthesis process in DELIGHT-SPICE [10]. To address the associated computational cost, a two-stage optimization strategy was later proposed [11], where equation-based optimization is applied in the first stage, followed by SPICE simulation to ensure accuracy. In another simulation-based tool [12], parallel simulations are carried out with different workstations for the purpose of time-saving. Following initial automation attempts, the effectiveness of evolutionary algorithms in analog/RF integrated circuit synthesis has been extensively explored. At the same time, the practice of multi-objective optimization has gradually been adopted in analog/RF integrated circuits. A multi-objective optimization tool has been proposed in [13], where a genetic algorithm searches for optimal solutions under specified design constraints for a folded-cascode amplifier. The Non-dominated Sorting Genetic Algorithm-II (NSGA-II) [14] has been utilized as the optimization kernel to solve both multi- and many-objective amplifier design problems proposed in [15]. Another multi-objective optimization tool [16] explores the performance space using the obtained pareto optimal front (PoF). Active filter and amplifier circuits have been synthesized, considering layout issues, where layout-aware models are used as performance estimators. GENOM-POF [17] employs NSGA-II to obtain optimal solution sets for two operational amplifiers under process variations. In addition, swarm intelligence (SI) algorithms are widely applied to analog/RF sizing problems. Some analog/RF circuits have been automatically sized by equation-based approaches, where particle swarm optimization (PSO) [18] has been used as the searching algorithm [19,20]. The proposed tool in [21] synthesizes an analog buffer, Miller OTA, and two-stage amplifier using ant colony optimization as the core algorithm [22], and constructs ADCs from the automatically sized sub-blocks. The simulation-based optimizer in [23] combines simulated annealing with particle swarm optimization (PSO) to avoid local optima. Performance evaluations of other swarm intelligence algorithms for analog/RF circuit synthesis are reported in [24]. Additionally, a butterfly-inspired optimization algorithm has been applied as the kernel for both single- and multi-objective analog amplifier design [25].

The progress in developing reliable and high-precision design automation tools has led to the exploration of innovative methods for efficiently synthesis more complex analog/RF circuits and systems. Single- and multi-objective optimization has been applied to a low-noise amplifier (LNA) in [26]. The inductors are selected from the solution database from the obtained pareto surface at the sizing phase, which ensures both efficiency and accuracy. Parasitic-aware sizing methodology is presented in [27], where floorplan constraints, layout constraints, and design constraints are handled by equation-based optimization using genetic programming. Post-silicon validation was presented for the two-stage amplifier, the voltage comparator, and the LNA. In [28], the authors highlight the use of inversion coefficients over simple analytic conditions to define transistor operation regions, enabling efficient optimization with faster convergence and improved cost functions in amplifier, LNA, and oscillator designs. In another RF sizing example, cross-coupled CMOS LC oscillator topologies have been compared based on their synthesis results [29]. A simulation-based, layout-aware approach utilized the Strength Pareto Evolutionary Algorithm 2 (SPEA-2) [30] to explore the solution space, with post-silicon measurements validating the synthesis outcomes. In [31], a four-stage amplifier has been successfully sized by adjusting the mutation rate, whereas the unmodified algorithm failed to converge.

In the last decade, the automatic synthesis of ICs has undergone a major transformation driven by advances in machine learning. Neural-network-based methodologies have enabled the synthesis of highly complex circuits under strict design constraints while significantly reducing design time compared to conventional flows. For instance, the ESSAB optimization tool [32] exploits ANN models trained on relatively small datasets, which are subsequently integrated into the optimization loop to improve efficiency. The tool has been validated by synthesizing operational amplifiers with stringent specifications in nearly half the time required by traditional approaches. Extending this line of research, the ANN-based intellectual property (IP) construction method introduced in [33] employs ANN modules as performance estimators within the optimization loop, with model accuracy verified through Pareto-optimal quality metrics.

Following these developments in synthesis, variation modeling has emerged as an equally critical research direction. Process variations have been incorporated into the optimization loop using deep neural networks (DNNs), thereby alleviating the prohibitive simulation costs of Monte Carlo analysis [34]. DNNs have also been employed to enhance the efficiency of global optimum searches [35]. Surrogate modeling represents another approach to accelerate optimization, where Gaussian regression processes are combined with physics-based device models and circuit performance equations [36]. This methodology not only reduces computational burden but also increases flexibility in the design process. A constrained multi-objective Bayesian optimization framework has further been proposed in [37], where circuit evaluation is carried out using Gaussian Processes. In parallel, artificial neural networks (ANNs) [38] have continued to expand their role in analog/RF circuit modeling, supporting both efficient variation-aware optimization and scalable design automation.

All of these developments have opened the way for the hierarchical synthesis of analog/RF systems. Researchers are increasingly relying on sophisticated modeling techniques as well as intelligent searching algorithms. As an early attempt at hierarchical design automation, [39] has introduced a two-step hierarchical synthesis approach that does not use an ANN. The lowest-level syntheses were performed based on cost function values obtained from system-level optimization. An amplifier and a second-order Butterworth filter have been chosen as case examples. Even if modeling techniques promise to facilitate top-level synthesis, dataset generation and model construction phases may be cumbersome for highly complex systems. Building on this, a different approach for system-level modeling was proposed for analog-mixed signal (AMS) circuits in [40]. Sub-blocks of the AMS circuits have been individually modeled and connected instead of constructing a big model for the entire system. Another approach was presented in [41], where some amplifier and ADC topologies have been modeled using the bottom-to-top methodology. The challenges associated with hierarchical synthesis can be alleviated through advanced intelligent modeling techniques. [42] introduces a bottom-to-top automation approach based on neural network (NN) modeling. Following the data generation process initiated with the simulation output, the dataset was expanded with the help of AI models. The developed tool first determines the circuit topology, then sizes the components, and finally produces the completed design. As case studies, a three-stage amplifier, a low-pass filter, a high-pass filter, and a band-pass filter have been considered. In [43], the $\Delta \Sigma$ modulator, a widely used architecture for analog-to-digital and digital-to-analog conversion, has been modeled and synthesized at the system level. The modulator model has been trained using data generated by the behavioral circuit model implemented in Simulink. The use of ANN in synthesis has been reported to significantly reduce the synthesis time. [44] proposes a successive-approximation (SAR) ADC compiler. The compiler determines design specifications at the component level according to the predefined system-level specifications. Bayesian optimization was employed to size the analog components. In addition to analog high-level circuit optimization, hierarchical synthesis of RF systems also appears in the literature. The matrix mapping technique has been used to handle hierarchical sizing of the RF front-end circuit [45]. Automation begins with inductor-level synthesis, where a surrogate model assesses the performance of the device. System-level synthesis proceeds with a bottom-up hierarchical methodology; each sub-block synthesized at the lower level is combined with mapping at the upper level. Another RF system synthesis approach can be found in [46], where the burden of EM simulation is eliminated thanks to the offline component library. Top-level optimization has been achieved by leveraging the Pareto optimal fronts (PoFs) of the sub-blocks. Also, in [47], a MATLAB model replaces the EM simulation for the inductor synthesis, which is the lowest level. The system-level circuitry is optimized with existing PoFs from previous levels. Even though the hierarchical automation approaches proposed in the literature are promising, they are not yet fully mature due to the challenging trade-off between efficiency and accuracy. This paper presents a hierarchical synthesis flow supported by neural network modeling. Both an analog and an RF system were synthesized using bottom-to-top and top-to-bottom design strategies, where pretrained ANN models were employed to predict design specifications. The primary contributions of this work can be summarized as follows:

• In addition to system-level modeling, sub-blocks were modeled individually, enabling rapid mapping between circuit parameters and top-level specifications.
• All circuits were modeled bidirectionally (from design parameters to specifications and vice versa), regardless of their position in the hierarchy, thereby facilitating the exploration of new regions in the solution space with minimal effort.
• To the best of our knowledge, the proposed method is the first simulation-free solution once the framework has been constructed.
• Once all the models are available, the time-to-design takes less than one second.
• Under changing design conditions, sub-block circuits can be re-optimized within a short time using the trained models, enhancing design flexibility at the system level.
• The proposed methodology was validated on two diverse and complicated circuits: 8-Bit ADC and RF receiver.

The remainder of the paper is organized as follows. Section 2 introduces the proposed hierarchical synthesis approach. Section 3 and Section 4 describe the modeling techniques through case study circuits. Experimental results for these circuits are presented in Section 5. Section 6 evaluates the effectiveness of the proposed method by comparing it with previously published hierarchical automation approaches. Finally, Section 7 concludes the paper.

2. Hierarchical Automation through ANN-Based Reusable Sub-Block Modeling

Our proposed hierarchical method comprises three main stages: circuit sizing and dataset construction, sub-block modeling, and system-level modeling. After establishing the top-level and bottom-level circuit models, hierarchical synthesis becomes versatile.

2.1. Approach Overview

The proposed three-step hierarchical automation approach, illustrated in Figure 1, begins with sub-block optimization and proceeds to ANN modeling. First, the user determines the optimization parameters and provides the circuit netlist along with appropriate testbenches to initiate lowest-level synthesis. Each sub-circuit is synthesized separately, and the dataset for the circuit-level modeling is constructed simultaneously within the loop. Circuit modeling is performed bidirectionally, like in [48], where the Pseudo-Designer receives design specifications obtained from simulation results as input data to predict appropriate device sizes, while the Pseudo-Simulator works in reverse manner to generate simulation results based on device sizes. This bidirectional modeling idea is the keystone for our hierarchical synthesis scheme because it remarkably speeds up performance evaluation. Following these steps, all solutions from the distinct PoFs are combined using the cross-product method to generate a comprehensive dataset for the entire system. System-level models are then created as the final task. At the end of the process, the sub-circuits can be rapidly re-generated, even when system-level design requirements change. Thus, the top-level design can be optimized within a short time since simulation-free lowest-level circuit models are available.

2.2. Circuit Sizing

A single/multi-objective optimization for analog/RF circuit sizing problems can be expressed as

$$\begin{array}{cc}Minimize& f_1\left(x\right),f_2\left(x\right),\dots ,f_m\\ Subjectto& g_j\left(x\right)\ge 0or{g}_j\left(x\right)\le 0\\ & x_i^L\le x_i\le x_i^U,\\ & \forall m\in 1,2,\dots ,M\\ & \forall j\in 1,2,\dots ,K\\ & \forall i\in 1,2,\dots ,N\end{array}$$

(1)

where design variables are represented as a vector x, bounded within the upper and lower limits of the search space. The vector $f\left(x\right)$ contains m objective functions, while $g\left(x\right)$ represents k constraints. When searching for a single optimal solution, either a single performance specification or a mathematical combination of multiple specifications is minimized or maximized through single-objective optimization. On the other hand, multi-objective optimization generates a solution set by exploring trade-offs among two or more objectives. The Pareto Optimal Front (PoF) represents these trade-offs, consisting of non-dominated solutions where enhancing one objective requires sacrifices in others. Both objective and constraint dominance rates can be used in selecting the solutions that constitute the PoF. The Non-Dominated Sorting Genetic Algorithm II (NSGA-II) adopted from [49] explores the search space to identify optimal candidate solutions for constructing the Pareto optimal front, employing genetic operations such as mutation, recombination, and selection to evolve successive generations. The first generation is randomly generated, and each subsequent generation is populated with twice as many individuals as the population size. To achieve minimization, the algorithm ranks solution sets based on Pareto dominance and selects individuals from the population accordingly. While performing minimization, the crowding distance operator guides selection mechanisms to obtain a uniformly distributed PoF. Since most real-world problems require constraint handling, the tournament selection mechanism contributes PoF ranking considering the constraints in the optimization process [14].

2.3. ANN Modeling

ANNs are inspired by the structure of the biological nervous system and are used to model phenomena exhibiting input–output correlations. A typical ANN model is illustrated in Figure 2, where neurons are arranged in multiple layers and concatenated layers form the whole network. Each neuron produces an output by applying a weighted summation to its input values. An optimizer adjusts these weights to train the network accurately.

Model construction generally comprises three distinct phases: dataset creation, model training, and testing. Dataset creation is a pivotal step to achieve good model performance. Meaningless or spatially clustered datasets can negatively impact the accuracy of the model. Some considerations should be taken into account in this phase. During model training, hyperparameters are determined, including the number of hidden layers, the number of neurons per layer, the learning rate, and the batch size. Eventually, the trained model is tested using standard error metrics, including mean absolute error (MAE), mean absolute percentage error (MAPE), mean squared error (MSE), and root mean squared error (RMSE).

2.4. System-Level Synthesis

An analog/RF system typically consists of lower-level circuit blocks. System-level behavior is highly dependent on the performance of the lower-level blocks. To manage design complexity, the designer divides the entire system into functional blocks—a concept known as hierarchical design. There are two approaches for hierarchical design: bottom-to-top and top-to-bottom. Regarding bottom-to-top approach, the design starts at the lowest circuit level to achieve system-level requirements. After determining the requirements of the lowest-level circuit, each block is individually designed, optimized, and verified before integration. These steps are repeated iteratively until the overall system requirements are satisfied. On the other side, the top-to-bottom hierarchical approach starts with system-level specifications and proceeds downward through block-level to device-level design. The designer utilizes some prediction methods, such as analytical formulas or behavioral modeling, to determine block-level specifications. Each block is designed individually, while integration and full-system simulation serve as a feedback loop within the top-to-bottom approach.

Although these two approaches may appear to be completely opposite, their design methodologies are not necessarily contradictory from a traditional perspective. However, this situation is valid for our proposed hierarchical synthesis method illustrated in Figure 3, where all sub-blocks and the system are modeled in a bidirectional flow. Bottom-to-top synthesis begins with user-defined device sizing. Each sub-block’s pseudo-simulator model receives device sizes to predict low-level performance. The system-level model is then used to estimate the overall system performance based on these bottom-level predictions. In top-to-bottom synthesis, the user defines top-level design specifications, i.e., system requirements. In the second step, the top-level pseudo-designer estimates what the design specification of the sub-blocks should be. Finally, pseudo-designer sub-block models provide all device sizes and complete the synthesis process. With the help of our consecutive model prediction approach, system-level design can be efficiently realized using both hierarchical methodologies.

3. Case Study - I: Hierarchical Modeling of Flash ADC

An 8-bit flash ADC is considered an analog case study. As shown in Figure 4, flash ADC consists of four major parts: a sample-and-hold (S&H) circuit to improve precision, a resistor ladder that acts as a voltage divider, a comparator array for generating digital codes, and an encoder that converts the comparator outputs into a binary output code.

As stated earlier, the training datasets of the sub-blocks are constructed within their own synthesis loops. Dataset creation is crucial to achieve accurate modeling. In analog/RF circuit modeling, circuit performance is susceptible to environmental variables such as the technology node, load impedance, bias voltage, and bias current. Therefore, users must generate and organize appropriate training datasets. Various dataset generation approaches have been introduced in the literature [50], aiming to explore the design space as extensively as possible. In this work, we utilized the search capability of NSGA-II within the optimization loop, with SPICE simulation serving as the performance evaluator. Both feasible and infeasible solutions are included in the training dataset.

3.1. S&H Block: Differential Amplifier Modeling

An S&H circuit is an essential part of ADCs, enabling precise and stable sampling of the input signal. As shown in Figure 5, it consists of a switching element, a holding capacitor, and a buffer, which are responsible for sampling, holding, and delivering the signal to the next stage, respectively. A basic differential amplifier is used as the operational amplifier in a buffer configuration to convey the sampled signal from the transmission gate. The basic differential amplifier, which is the first sub-block of the ADC, has been synthesized over 100 generations with a population size of 100. The circuit is designed to drive a 0.5pF capacitive load and is powered by a 1.8 V symmetric supply. Transistor dimensions and bias resistor define the design space of the optimization problem, which aims to simultaneously maximize gain and bandwidth while satisfying power consumption and phase margin constraints. The resultant PoF is shown in Figure 6. A well-distributed set of solutions were obtained for the design objectives. A summary for the optimization and modeling of the first sub-block is tabulated in Table 1. The modeling is implemented in Python using the TensorFlow library. To minimize the loss function in the training phase, the Adam algorithm is utilized as the optimizer. A total of 19,500 data points were obtained during the synthesis phase within 15 minutes, all of which were verified using SPICE simulations. The dataset was divided into an 80% training set and a 20% testing set. While the pseudo-simulator was trained for 150 epochs, the pseudo-designer was trained for 200 epochs. The batch size was set to 16 for both models. The performance of the trained model was evaluated using the mean square error (MSE) metric. At the end of the training, the pseudo-simulator achieved an MSE of 0.03, while the pseudo-designer records an MSE of 0.04.

3.2. Resistor&Comparator Array: Comparator Modeling

To enable fast conversion, a flash ADC uses a bunch of comparators, where each threshold voltage level provided by a resistor ladder has its own comparator. For an N-bit ADC, $2^{N-1}$ resistors define the threshold levels, and $2^{N-1}$ comparators are used to produce a thermometer code. A representation of the resistor and comparator array for an N-bit ADC, along with the comparator schematic used in our case, is given in Figure 7. The differential amplifier with a cross-coupled active load forms the core of the circuit, and its bias current is provided by a current source regulated by an externally applied constant voltage. The inverter stage determines the final output of the signal from the common amplifier configuration. To evaluate propagation delay performance, a ramp signal with a slew rate of 4 V/$\mu$s is applied to the circuit input. The load capacitance is set to 0.5 pF, as in the previous sub-block. Transistor dimensions define the design space, where the differential pair shares equal widths, and all transistors have the same channel length. Comparator synthesis has been carried out over 150 generations with a population size of 100. Power consumption and delay are considered both objective and constraint functions. The obtained PoF is shown in Figure 8, where solutions are evenly distributed among the design objectives.

Optimization parameters and model features for the comparator circuit are listed in Table 2. The network hyperparameters are similar to those used for the amplifier, and a total of 19,500 data points were used to train models. Test set constitutes 20% of the total dataset. Pseudo-simulator and pseudo-designer were trained with 150 and 200 epochs, respectively. The comparator models show better accuracy than the amplifier models, with mean squared error values of 0.002 and 0.0008 for the simulator and designer models, respectively.

3.3. Priority Encoder: Verilog-AMS Modeling

The priority encoder, which is the last sub-block of the flash ADC, is used to convert the thermometer code generated by the comparator array into binary code. As the circuit functions digitally, it is modeled using Verilog-A, which allows the integration of analog and digital circuits within a single simulation. With the help of the Verilog-A model, the ideal encoder model was implemented without any performance degradation that might be caused by the digital part.

3.4. 8-Bit ADC: System Level Modeling

As mentioned earlier, the system-level dataset was obtained using the cross-product of sub-blocks, as illustrated in Figure 9.

Consider a system consisting of two sub-blocks, each having three non-dominated Pareto-optimal solutions. Initially, the first solution of the first sub-block is combined sequentially with each solution of the second sub-block. The second and third solutions of the first sub-block follow the same procedure until all possible combinations are obtained. This process can be thought of as a nested for-loop. In general, when the system contains n sub-blocks, each with m Pareto-optimal solutions, the cross-product generates $m^n$ data points. In our ADC case, combining two analog sub-blocks with 100 solutions each yields a dataset of 10,000 simulation results. The dataset was split into 80% training data and 20% test data. The simulator model takes op-amp specifications (DC gain, bandwidth, phase margin, power consumption) and comparator specifications (delay, power consumption) as inputs. Conversely, the designer model predicts these specifications based on the requested best straight line Integral Non-Linearity (INL) — defined as the deviation of the ADC’s actual transfer function from the closest straight-line approximation — and Differential Non-Linearity (DNL). Dropout layers with a rate of 30% are inserted between dense layers to mitigate overfitting. Input neurons and output neurons were determined by the number of design specifications. As seen from the Table 3, the simulator model has 6 input and 2 output neurons, while the designer model has 2 input and 6 output linear neurons. The models were trained for 200 epochs with a batch size of 16, using the Adam optimizer. MSE values were measured as 0.01 and 0.005 for the simulator model and the designer model, respectively. Although dataset generation is time-consuming, a trained model can be reused repeatedly to obtain the desired solutions. Furthermore, the accuracy of the models can be enhanced by expanding the dataset using the sub-block models, which can be accomplished in a short time.

4. Case Study - II: Hierarchical Modeling of Generic Heterodyne Receiver

A block schema representation of a generic RF receiver is given in Figure 10. First, a band-pass filter selects the fundamental frequency and suppresses the interference occurring at the sidebands of the RF signal received from the antenna. The LNA amplifies the weak RF signal, which is then combined with the local oscillator (LO) signal in a mixer to produce an intermediate frequency (IF) output. The simulation of RF circuits is complex because it requires specialized analyses, and the circuits typically include passive devices. Generally, an electromagnetic (EM) simulator is utilized to evaluate RF circuit performance accurately. However, EM simulation is highly time-consuming, making it impractical for use in a synthesis loop. To address this, layout-aware parasitic models for passive elements were incorporated, as proposed in [29], where layout representations and equivalent circuit models are shown in Figure 11. The design parameters of the capacitor model are the metal width (W), length (L), and well spacing ($D_x$ and $D_y$), whereas the inductor has more parameters due to its complex nature, including the metal width (W), number of turns ($N_t$), outer diameter ($D_o$), spacing (s), and well spacing ($D_x$ and $D_y$). For rapid performance evaluation, HSPICERF^® is employed in the optimization loop, with equivalent circuits of passive devices included as subcircuits in the netlist during RF circuit simulations.

4.1. Low Noise Amplifier

The schematic of the LNA, the first building block of the receiver, is shown in Figure 12. The circuit operates at 2.2 GHz, determined by the inductor connected to the output port and the parasitic capacitance at the drain of the output transistor. Input and output are blocked by DC-blocking capacitors to prevent DC from entering the RF path. Design parameters, objectives, constraints, and the network structures of the LNA circuit are tabulated in Table 4. The algorithm searches for optimal solutions within the solution space, where noise figure and power consumption exhibit a trade-off relationship. Power consumption and S-parameter constraints define feasible and infeasible regions within the solution space. LNA synthesis was performed over 500 iterations with a population size of 50. Resultant PoF is given in Figure 13. Because the layout parameters of planar inductors complicate designer modeling, variations arise in the ANN architectures. For example, the pseudo-simulator model employs two hidden layers, whereas the pseudo-designer model uses three hidden layers with dropout regularization. In the simulator model, the input layer—corresponding to the output layer of the designer model—contains 20 neurons representing transistor dimensions, two resistor values, and the layout parameters of three planar inductors. The circuit design specifications are captured by five neurons.

A total of 24,750 data points obtained in the synthesis loop were used for the training. The simulator model was trained with 100 epochs and a batch size of 32, whereas the designer model, being more complex, was trained with 500 epochs and a batch size of 256. MSE was measured as 0.03 and 0.02 for the simulator model and the designer model, respectively.

4.2. Oscillator

A local oscillator generates a stable periodic signal, which is used to shift the incoming RF signal down to an intermediate frequency. The cross-coupled LC oscillator, chosen as the wave generator for our receiver study, is shown in Figure 14. The LC tank acts as the resonator, while the cross-coupled transistor pair provides negative impedance. The design space for optimization, listed in Table 5, includes transistor dimensions, the bias current, and the inductor and capacitor parameters.

Design objectives, constraints, and network structures for the oscillator circuit are listed in Table 6. Phase noise (PN) and power consumption were selected as objectives to be minimized, which were also treated as design constraints. Although the optimization objective is to minimize phase noise and power consumption simultaneously, a lower bound of -150 dBc/Hz for phase noise was imposed to prevent impractical designs. A narrow margin for the oscillator frequency was determined to achieve the targeted 2.4 GHz oscillation frequency. Moreover, the output signal was measured at multiple times during transient simulation to confirm sustained oscillation. The synthesis was performed over 400 generations with a population of 100. The obtained PoF is given in Figure 15. Both models consist of two hidden layers, while the number of neurons at the input and output layers varies depending on the modeling direction. A total of 34,705 data points were used for training over 100 epochs. MSE values were calculated as 0.02 for the pseudo-simulator model and 0.03 for the pseudo-designer model.

4.3. Mixer

A single balanced mixer topology, shown in Figure 16, was selected to realize signal conversion from RF frequency to IF frequency. The transistor pair produces the output signal based on the oscillation signal, while a single transistor converts the RF signal’s voltage into current. A 2.2-GHz sinusoidal signal with 0.1-V_peak amplitude was applied to the RF input, and a 2.4-GHz, 1-V_peak sinusoid was applied to the local-oscillator (LO) port. The transistor pair (M1 and M2) and the current-source transistor (M3) were externally biased to ensure operation in the proper region. The conversion gain (CG), defined as the ratio of the output IF signal voltage to the input RF signal voltage, was selected as the primary design objective. To assess the linearity of the mixer circuit, the third-order intercept point (IP3) was considered as the second objective function. In addition, the power consumption was constrained to be less than 10 mW. Optimization and modeling parameters of the mixer circuit are summarized in Table 7. The design space, defined by transistor dimensions and resistor values, is explored by the algorithm to identify the best trade-offs between conversion gain and IP3. The circuit was synthesized with 400 generations for 100 population size. The resulting PoF is shown in Figure 17, with the solution set reduced to facilitate dataset generation for the receiver system. The pseudo-simulator model of the mixer comprises two hidden layers, whereas the pseudo-designer model consists of three hidden layers, each followed by a dropout layer due to its higher complexity. The simulator model was trained for 300 epochs with a batch size of 32. On the other side, the training was performed with an epoch size of 250 and a batch size of 256 for the pseudo-designer model, using a total of 40,000 data points. The mean squared error (MSE) was calculated as 0.07 for both models.

4.4. Heterodyne Receiver: System Level Modeling

The dataset for the system level was obtained by combining the Pareto-optimal solutions of LNA, oscillator, and mixer circuits. Given that the number of solutions in the LNA PoF, oscillator PoF, and mixer PoF are 50, 67, and 12, respectively, the total size of the training dataset is calculated as 50 × 67 × 12 = 40,200. The dataset generation process requires approximately 32 hours, as each simulation takes nearly 3 seconds, while the time needed for model training is negligible. The obtained dataset was split into 80% training and 20% testing. The input vector consists of the receiver’s IP3 and conversion gain, while the output neurons of the receiver designer model include: S-parameters, power consumption, and noise figure from the LNA; phase noise, peak output amplitude, and oscillation frequency from the oscillator; and IP3 and conversion gain from the mixer. In the case of the pseudo-simulator model, the roles of the input and output vectors are reversed. The ANN structures for both directions are summarized in Table 8. Both the simulator model and the designer model consist of 6 hidden layers, each containing 360 neurons. All hidden layers are activated by the ReLU function. Two dropout layers were inserted in the pseudo-simulator network: between the second and third hidden layers (dropout rate 0.45) and between the fourth and fifth hidden layers (dropout rate 0.25). For the designer model, a single dropout layer with a rate of 45% was applied. The training process was carried out for 300 epochs. MSE values were measured as 0.124 and 0.06 for the simulator model and the designer model, respectively.

5. Experimental Results: Hierarchical Syntheses

To demonstrate the effectiveness of the proposed methodology, the trained models were employed within the hierarchical design scheme. As mentioned previously, the designer determines the design specifications of the bottom-level blocks to satisfy the predefined top-level system requirements in a bottom-to-top hierarchy. Conversely, when following the top-to-bottom direction, the device sizes of the individual components within the sub-blocks can be predicted. Although behavioral modeling is highly beneficial for accelerating the hierarchical design process, the user must still evaluate whether the specified design requirements are feasible for the given circuit or system topology and design space. Taking this into account, we selected design variables within the feasible region as model inputs. To assess the performance of the hierarchical pseudo-simulator model (referred to as the bottom-to-top modeling approach), five independent system-level designs were selected from the dataset formed by combining all solutions from the preexisting PoFs. In fact, determining the design parameters in the initial phase is challenging and cannot cover the entire solution space. Therefore, the pseudo-designer model (referred to as the top-to-bottom modeling approach) provides a promising alternative, as it predicts design parameters to achieve the targeted performance. Unexplored possible design areas in the solution space can be discovered by generating new designs beyond precedent solutions.

Although the model accuracy is commonly assessed using loss functions such as mean squared error, mean absolute error, or smooth absolute error, a more reliable measure is obtained by evaluating the performance of the model under independent environmental conditions. Since our proposed hierarchical synthesis approach relies on trained models, the accuracy of these models directly affects the success of the synthesis process. An illustration of the ANN-based hierarchical synthesis methodology is given in Figure 18. The hierarchical synthesis can be viewed as consisting of two distinct flows: the model-based top-to-bottom approach (right-hand side of the figure) and the model-based bottom-to-top approach (left-hand side of the figure). In the top-to-bottom hierarchical synthesis flow, the user first provides system-level design specifications. Based on these inputs, the model predicts the sub-block specifications needed to satisfy the top-level requirements. The most relevant solution from the PoFs is selected for each sub-block, and all selected designs are combined into a SPICE netlist for the final simulation. However, the bottom-to-top synthesis approach is slightly different. Pre-optimized sub-block solutions are forwarded to the upper level, and a pseudo-simulator model predicts the system-level specifications from their design specifications. Based on these performance values, the model iteratively receives the sub-block design specifications as input and predicts the corresponding system-level performance until the targeted specifications are achieved.

5.1. Hierarchical Synthesis of 8-Bit Flash ADC

To realize top-to-bottom hierarchical synthesis using the proposed approach, five independent system-level design specifications were determined. The results are listed in Table 9. Here, the term “obtained specification” refers to the SPICE validated system-level synthesis, performed using the pseudo-designer model. The relative percentage errors for INL and DNL indicate that the model maintains an accuracy of over 80% even in the worst-case scenario. It can be concluded that an ADC can be designed in under one second without sacrificing effectiveness.

To evaluate the performance of the bottom-to-top approach, five independent syntheses were performed, and their results are listed in Table 10, where INL and DNL values below 0.5 LSB were defined as design constraints. Furthermore, since the ADC has an 8-bit resolution, the complete set of 256 output codes must be retained without loss. Synthesis continued until the design specifications were met, requiring approximately 200 independent iterations. Even if all possible PoF solutions are combined, the synthesis will take less than 3 hours. To demonstrate the effectiveness of the synthesis, a selected solution from the results was validated through SPICE simulation, and the corresponding transient response is presented in Figure 19. The response time of the comparator plays a critical role in the lower bits, since a slow transition can result in the loss of multiple output codes. Moreover, aspects of the testbench configuration can be inferred from the transient output. At first glance, the conversion appears to have been performed correctly. However, this observation alone is insufficient to assess the performance of the ADC; further analysis is needed. The transfer function shown in Figure 20 was used to evaluate the resolution, monotonicity, and overall performance of the converter by measuring Integral Nonlinearity (INL) and Differential Nonlinearity (DNL). DNL measures the deviation of the two adjacent digital codes from the ideal Least Significant Bit (LSB) step, while INL evaluates the cumulative deviation of the transfer function from the linear response. The largest deviation among all output codes is reported as the DNL of the design. On the other hand, INL error was measured using the best straight line method. The selected result, whose SPICE outputs are given, exhibits an INL of 0.49 LSB and a DNL of 0.2 LSB, with a total of 256 output codes.

5.2. Hierarchical Synthesis of Heterodyne Receiver

To realize the hierarchical synthesis of the receiver front-end circuit, both sub-models and system-level models were trained. As discussed earlier, during frequency conversion, the mixer is expected to transfer the RF input signal power efficiently to the intermediate frequency (IF) output, achieving a high conversion gain. At the same time, it must maintain the linearity, ensuring minimal distortion and avoiding significant degradation in metrics such as IP3. Therefore, conversion gain and IP3 were chosen as the design objectives for the receiver. The synthesis results of the receiver circuit are given in Table 11 for both approaches. Five independent runs were performed to demonstrate the synthesis performances. Appropriate designs were successfully selected according to the design requests almost instantaneously, thanks to the receiver pseudo-designer. Additionally, SPICE simulations indicate that the worst-case error between the design requests and the SPICE validation of the synthesized designs remained below 15%. On the other side, the simulator model of the receiver explores all possible candidates to find those that meet the predetermined specifications. For the bottom-to-top synthesis, identical design constraints were imposed on both conversion gain and IP3, requiring that each remain greater than –10 dB. The required solutions were obtained within an acceptable time duration. In the worst-case scenario, when all possible combinations were explored to satisfy the design specifications, the model completed the process within 40 minutes.

Transient simulation of a chosen design from the bottom-to-top synthesis result is shown in Figure 21. A sinusoidal signal with an amplitude of 50 mV was applied to the RF input, and the oscillator outputs were connected to the local oscillator ports of the receiver. At the output port, the modulated signal resulting from the mixing of the input and oscillator signals was obtained. It is also worth noting that DC offsets of 0.5 V and 1 V were applied to the relevant receiver ports to ensure proper operation. Although the transient simulation shows that the input signal was modulated, Fourier analysis in the frequency domain is necessary to evaluate the conversion performance. The Fast Fourier Transform (FFT) plots of the selected design are given in Figure 22. To determine the conversion gain from the RF signal to the IF signal, an FFT was performed on both the input and output voltage waveforms. The gain was calculated as -6.87 dB from the ratio of the IF output magnitude and the RF input magnitude. Linearity was evaluated using the IP3 metric, where the power levels of the fundamental tones and the third-order intermodulation products were obtained through FFT analysis. The IP3 was calculated as –8.65 dB.

6. Discussion

The comparison presented in Table 12 highlights both quantitative and qualitative dimensions of the proposed method relative to existing hierarchical design approaches. One of the most prominent aspects is the flexibility in synthesis direction. Unlike prior methods, which typically adhere strictly to either a top-to-bottom or bottom-to-top strategy, the proposed approach supports bidirectional synthesis. This capability makes the method more adaptable to varying circuit complexities and design requirements, positioning it as a strong candidate for diverse applications. Another distinctive feature of the proposed method lies in its sub-block-based architecture. Each system-level circuit is decomposed into sub-blocks, with each sub-block supported not only by models but also by solutions from pre-existing PoFs. This dual structure enables the method to function as a backup-enabled system, meaning that if one synthesis path faces constraints or inaccuracies, alternative pathways remain accessible through pre-existing PoFs. From an algorithmic perspective, the integration of EAs alongside ANNs reflects a modern, hybridized approach to design automation. This combination allows the method to benefit from both data-driven generalization and algorithmic adaptability, aligning with the trend of next-generation design methodologies that prioritize scalability and adaptability. The proposed method is competitive in terms of accuracy; however, since sub-block optimization and dataset generation for system-level circuits require considerable time, it may be regarded as computationally heavy (still faster than a designer). Nevertheless, once the model is trained, it can be reused to target different specifications efficiently.

7. Conclusion

Electronic design automation facilitates the design of analog/RF circuits by significantly reducing the required design time. While individual sub-blocks of a system (e.g., amplifiers, oscillators, voltage comparators) can be synthesized without much difficulty, automation becomes increasingly challenging as circuit complexity grows toward the system level. To address this, hierarchical automation approaches have been presented based on the principles of traditional hierarchical design. However, achieving highly flexible automation with minimal human intervention remains challenging, as balancing the trade-off between accuracy and efficiency is still an open problem. In this paper, we introduce an ANN-powered bidirectional hierarchical automation methodology. First, system-level circuits were partitioned into sub-circuits and synthesized using a multi-objective optimization tool. Second, each block was modeled for both bottom-to-top and top-to-bottom flows, with a dataset automatically generated within the optimization loop. Finally, system-level circuits were modeled using simulation data obtained through a cross-product method that included all possible combinations of sub-block solutions. The proposed approach demonstrates that integrating ANN into the hierarchical flow can provide a complementary framework that leverages the predictive capabilities of neural networks while preserving the structured advantages of the hierarchical design methodology. Additionally, pseudo-simulator and pseudo-designer models enable system-level automation for both flows. This bi-directionality increases design flexibility, as specifications can be propagated in either direction depending on design needs. Once all circuit levels are modeled, hierarchical synthesis can be performed. To achieve bottom-to-top synthesis, the pseudo-simulator model is employed to predict system-level requirements based on the design specifications. Conversely, in the top-to-bottom flow, the designer model estimates sub-block specifications to satisfy user requests. If the sub-block designs predicted by the system-level model are not available in the pre-existing solutions, the lower-level circuits can be rapidly re-optimized to satisfy system-level requirements by leveraging pre-trained ANN models. SPICE simulations validated that the proposed methodology enables system-level synthesis of a full-flash ADC and a receiver front-end circuit, achieving over 95% accuracy within practical time frames. To the best of the authors’ knowledge, this is the first paper to perform hierarchical optimization using ANN at all circuit levels. The next step for the method, which remains open to further development, is expected to be hierarchical synthesis with topology-independent modeling.