Black-Box Modeling Approach with PGB Metric for PSRR Prediction in Op-Amps

1. Introduction

The swift advancement of electronic technology has given rise to the necessity for low-power and high-performance circuit design [1,2,3,4]. In this context, fundamental building blocks of any chip, such as operational amplifiers, low-dropout regulators (LDOs), and bandgap references, have become increasingly important. Maintaining circuit stability under diverse operating conditions thus becomes critical. The PSRR serves as a key metric for assessing a circuit’s ability to suppress power supply noise, directly impacting signal integrity and system stability. In the realm of high-precision medical devices [5], enhancing the PSRR augments measurement precision and diagnostic reliability. In high-speed communication systems, it attenuates noise interference during data transmission. And in portable devices, it prolongs battery life and enhances immunity to interference.

Conventional PSRR calculation methods rely predominantly on simplified analyses of system poles and zeros, often using low-frequency equivalent circuit models [6,7,8]. However, as circuits operate at higher frequencies, parasitic capacitance, inductance, and other high-frequency effects introduce significant deviations between calculated and actual performance. This discrepancy becomes even more pronounced in radio frequency (RF) and high-speed communication circuits, where complex interactions between power supply noise and parasitic parameters exacerbate the issue. Moreover, existing methods lack a unified theoretical framework and standardized calculation process, forcing designers to invest substantial time in theoretical derivation and experimental validation when addressing novel circuit architectures. Such constraints hinder design efficiency and innovation.

Researchers have proposed various circuit-level techniques to improve PSRR, but each comes with shortcomings that underscore the need for a general modeling approach. For instance, Kim introduced an NMOS LDO regulator with an intrinsic gain-tracking ripple cancellation technique to achieve high PSRR [9]. Similarly, Zhang employed a chopper stabilization scheme in a Class-D audio amplifier to maintain a high PSRR across the entire audio band [10]​. While effective, such solutions are tailored to specific applications (voltage regulators or amplifiers) and do not provide a broadly applicable theory for PSRR prediction. In addition, many designs still struggle to sustain high PSRR at elevated frequencies. For example, an output-capacitor-less LDO designed for ultra-low voltage achieved only about 30 dB PSRR at 10 kHz​, illustrating how traditional design techniques can fall short in high-frequency or low-headroom scenarios [11]. These recent works demonstrate the importance of PSRR optimization but also highlight the inadequacy of existing methods to generalize across different circuits and operating conditions. A more universal modeling approach is needed to predict and optimize PSRR from DC up to the mid-frequency range in a systematic, time-efficient manner.

To address these challenges, we propose a black-box modeling approach for PSRR prediction in multi-stage op-amps. The core idea is to collapse the multi-stage amplifier into a simplified equivalent model using Thevenin’s theorem, treating the first amplification stage as an abstracted black box. By deriving the Thevenin-equivalent output of the first stage and reintegrating it into the overall circuit, the PSRR calculation is greatly simplified without sacrificing accuracy​. This approach yields an analytical yet intuitive understanding of how each stage contributes to the overall PSRR, and it naturally incorporates important design parameters such as pole-zero locations and gain-bandwidth limits​. Compared to brute-force simulation or complex small-signal models, the black-box method significantly reduces the mathematical effort required to evaluate PSRR, making it accessible for early-stage design and optimization.

In addition, we introduce a new metric called the Power-Supply Rejection Gain-Bandwidth (PGB) product to characterize high-frequency PSRR behavior. By analogy to the op-amp gain-bandwidth product, the PGB is defined as the product of the DC PSRR value and the frequency of the dominant PSRR zero​. This metric captures the fundamental trade-off between low-frequency suppression and the frequency range over which that suppression is effective. A higher PGB indicates that the PSRR remains strong over a broader bandwidth, whereas a lower PGB means the PSRR begins to deteriorate at a lower frequency. Using the PGB metric, one can more intuitively analyze the design trade-offs between PSRR and other performance parameters (such as stability or bandwidth) within the target frequency range. An important advantage of the PGB-based evaluation is that it avoids the need for tedious high-frequency small-signal modeling (e.g. large matrix S-parameter analysis). Instead, the PSRR and first-pole characteristics are extracted directly to yield an efficient, first-order prediction of PSRR performance across frequency​. The proposed method is applicable from DC up to the op-amp’s unity-gain bandwidth (UGB). Notably, it provides a unified explanation for why different circuit architectures with the same low-frequency PSRR and pole configuration can exhibit divergent PSRR roll-off behaviors as they approach the UGB​. For example, an LDO regulator and a two-stage op-amp (each optimized for similar DC PSRR) might have different PSRR values at mid-frequency (near their UGB), due to differences in internal gain distribution and zero/pole placement.

We validate the proposed method by analyzing typical circuit structures. The rest of this paper is organized as follows. Section II reviews the traditional PSRR calculation methods and introduces the theoretical basis of our method and details the PSRR calculation process and zero-pole characteristics of different circuits. Section III verifies the accuracy of PSRR calculation through the design and simulation of complex circuits and confirms the feasibility of optimizing PSRR through PGB calculation analysis. Finally, Section IV summarizes the advantages of the proposed method and outlines the direction of future research.

2. Materials and Methods

2.1. Related Work

We leverage Allen's interpretation of PSRR [7] and develop a "black-box" model that simplifies the intricate circuitry. This model is particularly applicable to Thevenin Equivalent Circuit Analysis, where the Thevenin theorem simplifies linear resistor networks with independent sources into a single voltage source in series with a resistance. Specifically, for any single-port network N, the port can be represented equivalently by a voltage source —whose value corresponds to the open-circuit voltage (u_oc)—in series with a resistance R_o, which is the equivalent resistance observed at the port when all independent sources are deactivated.

Figure 1. Thevenin equivalent circuit.

Figure 1. Thevenin equivalent circuit.

2.2. Proposed Methodology

In this section, we employ the proposed black-box theory to analyze the PSRR of various operational amplifiers.

2.2.1. PSRR Calculation for P-Input Two-Stage Op-Amps

Figure 2. Typical structure of a P-input two-stage op-amp.

Figure 2. Typical structure of a P-input two-stage op-amp.

In this op-amp, the input stage usually consists of two P-type MOSFETs (M₁ and M₂) that receive the input signal and provide initial amplification. Transistors M₃ and M₄ act as load devices and work in conjunction with M₁ and M₂ to enhance the gain of the input stage. Current mirrors comprising M₅ and M₇ supply a stable bias current to the input stage while ensuring that the currents in M₁ and M₂ are matched. In the output stage, transistor M₆ further amplifies the signal from the input stage and provides sufficient drive capability for the load.

To simplify the calculation, we treat the first stage of the op-amp as a “black box” with input terminals which denoted as $V_{in}$ and an output terminal which denoted as $V_{out}$. This is illustrated in Figure 3.

Figure 3. Two-stage op-amp circuit after “black-box” abstraction.

Figure 3. Two-stage op-amp circuit after “black-box” abstraction.

The processing of the first stage is performed in several steps:

a)

Evaluating the Impact of $V_{dd}$ on the Thevenin Equivalent Output Voltage of the First Stage

Figure 4. Thevenin equivalent circuit for the first stage of the op-amp.

Figure 4. Thevenin equivalent circuit for the first stage of the op-amp.

The first stage is viewed as an independent module. Based on the Thevenin theorem, the equivalent voltage generated by $V_{dd}$ is given by $V_{out1}=b_1{V}_{dd}$.

$$b_1\approx {\displaystyle \frac{1}{2g_{m3}{r}_{o5}}},$$

(1)

b)

Evaluating the Impact of $V_{in}$ on the Thevenin Equivalent Output Voltage of the First Stage

Figure 5. Thevenin equivalent output voltage of the first stage.

Figure 5. Thevenin equivalent output voltage of the first stage.

For a differential input $V_{in}$ , the corresponding Thevenin equivalent output voltage is:

$$V_{Thev,diff}={\mathrm{g}}_{m1}(r_{o2}||r_{o4}),$$

(2)

Likewise, for a common-mode input $V_{in}$, the corresponding Thevenin equivalent output voltage is:

$$V_{Thev,cm}=-{\displaystyle \frac{V_{in}}{\frac{g_{m3}}{g_{m1}}-2g_{m3}{r}_{o5}},}$$

(3)

$$V_{thevenin}=-{\displaystyle \frac{V_{in}}{\frac{g_{m3}}{g_{m1}}-2g_{m3}{r}_{o5}}},$$

(3)

The common-mode output voltage is relatively small and can be combined with the differential output voltage. Therefore, in the subsequent calculations, the common-mode contribution is typically neglected.

c)

Constructing the Thevenin Equivalent Circuit

Using the superposition theorem, the first stage is further simplified to a structure consisting of a voltage source and a resistor, as shown in the lower left area of Figure 6, where $R=r_{o2}\left|\right|r_{o4}$ represents the output resistance of the first stage.

d)

Deriving the PSRR Transfer Function

The equivalent circuit for the two-stage op-amp is shown in Figure 7. Considering the gate-drain capacitance C_gd of M₇, we use small-signal analysis to write the node current equations and thereby solve for the PSRR transfer function.

Moreover, in the PSRR transfer function derived from the black-box model, two primary zeros emerge, denoted Z1 and Z2. The first zero, Z1, corresponds to the frequency at which supply-induced noise contributions from the first and second amplifier stages cancel each other, resulting in a null (zero) in the PSRR response. The second zero, Z2, occurs at a higher frequency and typically arises from a secondary coupling mechanism or parasitic feedback path within the op-amp. For clarity in analysis, we assume Z1 lies at a lower frequency than Z2. This assumption isolates the low-frequency behavior dominated by Z1 and aligns with the typical frequency ordering in multi-stage analog circuits. Similarly, when examining the pole locations, we will assume a dominant low-frequency pole (p1 < p2) to maintain consistency in the frequency-domain analysis. With these definitions and assumptions in place, we now proceed to derive the DC PSRR value and identify the corresponding zero and pole positions. It should be noted that in common multi-stage amplifiers, the two zeros caused by the first-stage output and third-stage feedback equivalence usually satisfy Z1 < Z2.

First, we write the node current equation at node $V_1$:

$${\displaystyle \frac{(b_1{V}_{dd}+A{V}_o)-V_1}{R}}+s(V_o-V_1)C_c=V_{1}s{C}_1,$$

(4)

$$V_1={\displaystyle \frac{b{V}_{dd}+(A+Rs{C}_c)V_o}{1+Rs(C_1+C_C)}},$$

(5)

Similarly, writing the node current equation at node $V_o$:

$$(V_o-V_1)s{C}_C+g_{m6}{V}_1+{\displaystyle \frac{V_o}{r_{o6}}}+V_{o}s{C}_L={\displaystyle \frac{V_{dd}-V_o}{r_{o7}}}+(V_{dd}-V_o)s{C}_{gd7},$$

(6)

$$V_1={\displaystyle \frac{V_{dd}（\frac{1}{r_{o7}}+\mathrm{s}{C}_{gd7}）-V_o[(\frac{1}{r_{o7}}+\frac{1}{r_{o6}})+s(C_c+C_L+C_{gd7})]}{g_{m6}-s{C}_C}},$$

(7)

By equating (5) and (7):

$$V_1={\displaystyle \frac{V_{dd}（\frac{1}{r_{o7}}+\mathrm{s}{C}_{gd7}）-V_o[(\frac{1}{r_{o7}}+\frac{1}{r_{o6}})+s(C_c+C_L+C_{gd7})]}{g_{m6}-s{C}_C}}={\displaystyle \frac{b{V}_{dd}+(A+Rs{C}_c)V_o}{1+Rs(C_1+C_C)}},$$

(8)

$${\displaystyle \frac{1}{PSRR(s)}}={\displaystyle \frac{V_o}{V_{dd}}},$$

(9)

In the derivation above, it is assumed that $L_5=L_7$, due to matching requirements. if we set ${({\displaystyle \frac{W}{L}})}_7=M{({\displaystyle \frac{W}{L}})}_5$ and ${({\displaystyle \frac{W}{L}})}_6=N{({\displaystyle \frac{W}{L}})}_3$,we obtain that $I_7=M{I}_5$, $r_{o5}=M{r}_{o7}$, and:

$${\displaystyle \frac{g_{m6}{r}_{o7}}{2g_{m3}{r}_{o5}}}={\displaystyle \frac{1}{2M}}\sqrt{{\displaystyle \frac{K_n^{\text{'}}{(\frac{W}{L})}_6{I}_6}{K_n^{\text{'}}{(\frac{W}{L})}_3{I}_3}}}={\displaystyle \frac{1}{2M}}\sqrt{{\displaystyle \frac{{(\frac{W}{L})}_6}{{(\frac{W}{L})}_3}}\times 2M}=\sqrt{{\displaystyle \frac{N}{2M}}},$$

(10)

Next, we derive the DC PSRR value as well as the positions of the zero and pole:

$${\displaystyle \frac{1}{|PSRR(s)|}}={\displaystyle \frac{\frac{1}{r_{o7}}(1-\sqrt{\frac{N}{2M}})}{g_{m6}A+(\frac{1}{r_{o7}}+\frac{1}{r_{o6}})}}\approx {\displaystyle \frac{1-\sqrt{\frac{N}{2M}}}{A{g}_{m6}{r}_{o7}}},$$

(11)

Assuming Z₁ << Z₂, C_gd7 << C_C, C₁ << C_C, and for stability, we have $g_{m1}\ll g_{m6}$:

$$Z_1\approx -{\displaystyle \frac{\frac{1}{r_{o7}}(1-\sqrt{\frac{N}{2M}})}{\frac{R}{r_{o7}}(C_1+C_C)+C_{gd7}+b_1{C}_C}}\approx -{\displaystyle \frac{1-\sqrt{\frac{N}{2M}}}{R(C_1+C_C)+r_{o7}{C}_{gd7}}}\approx -{\displaystyle \frac{1-\sqrt{\frac{N}{2M}}}{R(C_1+C_C)}},$$

(12)

$$\begin{array}{l}{Z}_2\approx -{\displaystyle \frac{\frac{R}{r_{o7}}(C_1+C_C)+C_{gd7}+b_1{C}_C}{R{C}_{gd7}(C_1+C_C)}}\approx -{\displaystyle \frac{R(C_1+C_C)+r_{o7}{C}_{gd7}}{r_{o7}R{C}_{gd7}(C_1+C_C)}}\approx -{\displaystyle \frac{1}{r_{o7}{C}_{gd7}}}\\ \end{array},$$

(13)

Further assuming $P_1\ll P_2$, leads to:

$$\begin{array}{c}{P}_1\approx {\displaystyle \frac{-[g_{m6}A+(\frac{1}{r_{o6}}+\frac{1}{r_{o7}})]}{(g_{m6}-g_{m1})R{C}_C+R(\frac{1}{r_{o6}}+\frac{1}{r_{o7}})(C_1+C_C)+(C_{gd7}+C_L+C_C)}}\approx -{\displaystyle \frac{g_{m6}A}{(g_{m6}-g_{m1})R{C}_C}}\approx -{\displaystyle \frac{g_{m6}{g}_{m1}}{(g_{m6}-g_{m1})R{C}_C}}\approx -{\displaystyle \frac{g_{m1}}{C_C}}=\mathrm{GB},\end{array}$$

(14)

$$P_2={\displaystyle \frac{g_{m6}}{C_1+C{}_L+C_{gd7}}},$$

(15)

$${\displaystyle \frac{1}{|PSRR(s)|}}={\displaystyle \frac{1-\sqrt{\frac{N}{2M}}}{A{g}_{m6}{r}_{o7}}}\times {\displaystyle \frac{(1+\frac{Rs(C_1+C_C)}{1-\sqrt{\frac{N}{2M}}})(1+r_{o7}{C}_{gd7})}{(1+\frac{s}{GB})(1+s\frac{C_1+C{}_L+C_{gd7}}{g_{m6}})}},$$

(16)

The location of $Z_1$ is the closest to the origin relative to the first pole. Whether the DC PSRR value is positive or negative depends on the specific values of N and M When N is approximately twice that of M, the DC PSRR value becomes very high; however, the zero also shifts closer to the origin.

The PSRR is influenced by two signal paths within the op-amp. In the first path, the signal entering from $r_{o5}$ reduces the output voltage at low frequencies; in the second path, the signal entering from $r_{o7}$ has the opposite effect and increases the output voltage. For simplification, the drain of M₅ is grounded, thereby neglecting the signal contribution from M₅ and resulting in a positive DC PSRR gain. Under ideal bias current source conditions, if N is greater than twice that of M, the PSRR is negative; if N is less than twice that of M, the PSRR is positive. The location of the zero is also closely related to the ratio of these two parameters.

2.2.2. PSRR Calculation for N-Input Two-Stage Op-Amps 

In this subsection, we adopt a similar analytical approach to study the PSRR of N-input two-stage op-amps and thereby demonstrate the portability of the new PSRR calculation theory.

Based on the analysis in Section A for a typical P-input two-stage op-amp, we consolidate the simplified flowchart for a common N-input two-stage op-amp into a single diagram, as shown in Figure 9.

Figure 9. Simplified flow chart of a common N-input two-stage op amp.

Figure 9. Simplified flow chart of a common N-input two-stage op amp.

The following quantities are computed: the Thevenin equivalent voltage due to $V_{dd}$ from the first stage, the Thevenin equivalent voltage due to $V_{in}$, the PSRR, the DC PSRR value, the zero, the pole, and the PGB.

From Figure 9(b), the Thevenin equivalent voltage due to$V_{dd}$is given by $V_{out1}=b_2{V}_{dd}$. While:

$$b_2\approx {\displaystyle \frac{g_{m1}{r}_{o1}{r}_{o5}}{\frac{1}{2g_{m3}}+g_{m1}{r}_{o1}{r}_{o5}}}\approx {\displaystyle \frac{2g_{m1}{r}_{o1}{g}_{m3}{r}_{o5}}{1+2g_{m1}{r}_{o1}{g}_{m3}{r}_{o5}}}\approx 1,$$

(18)

Similarly, the Thevenin equivalent voltage due to $V_{in}$ is $A{V}_{in}$ :

$$A=g_{m1}(r_{o2}||r_{o4}),$$

(19)

Using the node current equations, we obtain

$$V_1={\displaystyle \frac{(b+Rs{C}_1)V_{dd}+(A+Rs{C}_C)V_o}{1+Rs(C_1+C_2+C_C)}},$$

(20)

$$V_o={\displaystyle \frac{V_{dd}(g_{m6}+\frac{1}{r_{o6}})+V_o[(\frac{1}{r_{o6}}+\frac{1}{r_{o7}})+s(C_C+C_L)]}{g_{m6}-s{C}_C}},$$

(21)

Equating (20) and (21) yields:

$$\begin{array}{l}{V}_o\{(g_{m6}-s{C}_C)（\mathrm{A}+Rs{C}_C)+[({\displaystyle \frac{1}{r_{o6}}}+{\displaystyle \frac{1}{r_{o7}}})+s(C_C+C_L)][1+Rs(C_1+C_C+C_L)]\}\\ =Vdd\{(g_{m6}+{\displaystyle \frac{1}{r_{o6}}})[1+Rs(C_1+C_C+C_L)]+(b_2+Rs{C}_1)(-g_{m6}+s{C}_C)\}\end{array},$$

(22)

PSRR Calculation:

Under the assumptions that $Z_1\ll Z_2$ ,$C_2\ll C_C$, approximate expressions for the DC PSRR value and the zero can be derived as

$${\displaystyle \frac{1}{|PSRR(s)|}}={\displaystyle \frac{\frac{g_{m6}}{1+2g_{m1}{r}_{o1}{g}_{m3}{r}_{o5}}+\frac{1}{r_{o6}}}{A{g}_{m6}+(\frac{1}{r_{o7}}+\frac{1}{r_{o6}})}}\approx {\displaystyle \frac{\frac{1}{r_{o6}}}{A{g}_{m6}}}={\displaystyle \frac{1}{A{g}_{m6}{r}_{o6}}},$$

(23)

$$Z_1\approx -{\displaystyle \frac{1}{g_{m6}{r}_{o6}R(C_2+C_C)}},$$

(24)

$$Z_2\approx -{\displaystyle \frac{g_{m6}}{C_1}},$$

(25)

Assuming that $P_1\ll P_2$,$C_L\ll C_C$,$C_1\ll C_C$, $g_{m1}\ll g_{m6}$, he pole of the PSRR is approximately given by:

$$P_1\approx -{\displaystyle \frac{g_{m6}}{C_C}}=GB,$$

(26)

$$P_2\approx -{\displaystyle \frac{g_{m6}}{C_1+C_2+C_L}}=GB,$$

(27)

$${\displaystyle \frac{1}{PSRR(s)}}={\displaystyle \frac{1}{A{g}_{m6}{r}_{o6}}}\times {\displaystyle \frac{(1+g_{m6}{r}_{o6}Rs(C_2+C_C))(1+s\frac{C_1}{g_{m6}})}{(1+\frac{s}{GB})(1+s\frac{C_1+C_2+C_L}{g_{m6}})}},$$

(28)

Similarly, the calculation of PGB follows the same procedure as described previously.

$$PGB=\left|Z_1\times PSRR\right|=\frac{1}{g_{m6}{r}_{o6}R\left(C_2+C_L\right)}\times A{g}_{m6}{r}_{o6}=\frac{g_{m1}}{C_2+C_L},$$

(29)

From (29), it is apparent that the PGB of the N-input is relatively smaller. It is evident that by increasing the output resistance R of the first stage and the small-signal resistance R_O6 of M₆, the DC PSRR value improves. However, the ${\omega }_{-3dB}$ point shifts closer to the origin, thereby enhancing only the low-frequency portion of the response, while the PGB remains unchanged. Under stability constraints, reducing C_C shifts ${\omega }_{-3dB}$ away from the origin and improves the frequency characteristics. Comparing the PGB values for the P-input and N-input two-stage op-amps (under ideal bias conditions), the frequency response of the P-input op-amp is superior by an order of magnitude.

2.2.3. P-Input Folded Cascode Op-Amps

The folded cascode structure is an efficient design for the op-amp input stage, significantly increasing the input impedance and gain while improving the power supply rejection. Following the approach used for the P- and N-input two-stage op-amps, we analyze the common P-input folded cascode op-amp structure and derive the relevant equations.

In Figure 10, the capacitor C2​ is a parasitic capacitor located between Vdd​ and Vo​. While it might seem counter-intuitive for achieving high PSRR due to its placement, C2​ actually plays a vital role in stabilizing the output voltage Vo​ by providing a low-impedance path for high-frequency noise and supply-induced disturbances. This helps in filtering out unwanted noise, which is crucial for improving the power supply rejection ratio (PSRR). Among all the parasitic capacitances present in the circuit, C2​ is considered the most significant due to its larger capacitance value and strategic position in the feedback loop, which maximizes its positive impact on PSRR enhancement.

Using the Thevenin theorem, we first derive the open-circuit output voltage of the first stage. This open-circuit voltage can be computed by applying the superposition principle. The analytical approach is similar to that for the P- and N-input two-stage op-amps. First, the effect of the drain input signal from M₅ on the output is calculated. The circuit is modeled using the small-signal equivalent, and further simplified via Norton’s theorem, as shown in Figure 11, yielding a Thevenin equivalent voltage of $V_{out1}=b_3{V}_{dd}$, and:

$$b_3\approx 0.5({\displaystyle \frac{1}{g_{m3}}}+{\displaystyle \frac{1}{g_{m6}}})\approx (1+{\displaystyle \frac{g_{m3}}{g_{m6}}}){\displaystyle \frac{1}{g_{m3}{r}_{o5}}},$$

(30)

Next, we calculate the effects of the drain input signals from M₃ and M₄ on the output. The resulting Thevenin equivalent voltage is $V_{out1}=m_1{V}_{dd}$.

$$m_1\approx {\displaystyle \frac{g_{m11}{r}_{o11}\times (0.5r_{o7})\left|\right|(g_{m1}{r}_{o1}{r}_{o5})}{0.5(\frac{1}{g_{m3}}+\frac{1}{g_{m9}})+g_{m11}{r}_{o11}\times (0.5r_{o7})\left|\right|(g_{m1}{r}_{o1}{r}_{o5})}}\approx {\displaystyle \frac{0.5g_{m11}{r}_{o11}{r}_{o7}}{0.5(\frac{1}{g_{m3}}+\frac{1}{g_{m9}})+0.5g_{m11}{r}_{o11}{r}_{o7}}}={\displaystyle \frac{g_{m3}{g}_{m11}{r}_{o11}{r}_{o7}}{g_{m3}{g}_{m11}{r}_{o11}{r}_{o7}}}$$

(31)

where it is found that $m_1\approx 1$.

Subsequently, the effect of $V_{in}$ on the output is computed; as shown in Figure 12, the Thevenin equivalent voltage induced by $V_{in}$is $-A{V}_{in}$ Finally, by applying the superposition theorem, the circuit is reduced to its simplest form:

Figure 12. Folded cascode op-amp simplified using the superposition theorem.

Figure 12. Folded cascode op-amp simplified using the superposition theorem.

$R=g_{m9}{r}_{o9}{r}_{o9}\Vert g_{m11}{r}_{o11}{r}_{o7}$ denotes the output resistance of the first stage. To calculate the PSRR, the values of $V_o$and $V_{dd}$ must be determined. Based on the circuit diagram, we write the node current equation at $V_o$:

$$\frac{|(b_3+m_1)V_{dd}-A{V}_o|-V_o}{R}+(V_{dd}-V_o)s{C}_2=V_{o}s{C}_1$$

(32)

which simplifies to:

$${\displaystyle \frac{V_o}{V_{dd}}}={\displaystyle \frac{(b_3+m_1)+Rs{C}_2}{(A+1)+Rs(C_1+C_2)}}\approx {\displaystyle \frac{1+Rs{C}_2}{A+Rs(C_1+C_2)}},$$

(33)

$\because b_3+m_1\approx 1$

$${\displaystyle \frac{1}{PSRR(s)}}={\displaystyle \frac{V_o}{V_{dd}}}\approx {\displaystyle \frac{1}{A}}\times {\displaystyle \frac{1+Rs{C}_2}{1+\frac{Rs(C_1+C_2)}{A}}}={\displaystyle \frac{1}{A}}\times {\displaystyle \frac{1+Rs{C}_2}{1+\frac{s(C_1+C_2)}{g_{m1}}}}$$

(34)

$${\displaystyle \frac{1}{|PSRR(s)|}}={\displaystyle \frac{1}{A}},$$

(35)

$$Z=-{\displaystyle \frac{1}{R{C}_2}},$$

(36)

$$P=-{\displaystyle \frac{g_{m1}}{C_1+C_2}},$$

(37)

In this example, $R=g_{m9}{r}_{o9}{r}_{o9}\left|\right|g_{m11}{r}_{o11}{r}_{o7}$. The inverse of the DC PSRR value is equal to the op-amp gain. The PGB is then derived as:

$$PGB=|Z\times PSRR|={\displaystyle \frac{A}{R{C}_2}}={\displaystyle \frac{g_{m1}}{C_2}},$$

(38)

Key design insights include:

a)

Increasing g_m1 directly raises the DC PSRR value.

b)

Reducing the parasitic capacitance C₂ improves the frequency response.

c)

The dominant pole of the op-amp is associated with its output node. Consequently, augmenting C₁ shifts this pole closer to the origin, which is advantageous for enhancing both system stability and the frequency response of the PSRR. However, it is crucial to strike a balance with the required bandwidth; one cannot indiscriminately reduce the bandwidth without considering the overall system performance requirements.

2.2.4. N-Input Folded Cascode Op-Amps

Following the approach in Section 2.2.3, we analyze the N-input folded cascode op-amp. The simplified flowchart for a typical N-input two-stage op-amp is consolidated in Figure 13.

Figure 13. Simplified flowchart for a typical N-input two-stage op-amp

Figure 13. Simplified flowchart for a typical N-input two-stage op-amp

From the Thevenin equivalent circuit, we obtain:

$$V_1=V_{dd}{\displaystyle \frac{g_{m1}{r}_{o1}{r}_{o5}}{0.5r_{o5}+g_{m1}{r}_{o1}{r}_{o5}}},$$

(39)

$$V_{dd}-V_1=V_{dd}{\displaystyle \frac{0.5r_{o5}}{0.5r_{o5}+g_{m1}{r}_{o1}{r}_{o5}}},$$

(40)

$$V_{open}=V_1-2g_{m11}(V_{dd}-V_1)\times 0.5r_{o11}=V_{dd}{\displaystyle \frac{g_{m1}{r}_{o1}{r}_{o5}-g_{m11}{r}_{o11}{r}_{o7}}{0.5r_{o7}+g_{m1}{r}_{o1}{r}_{o5}}}\approx V_{dd}(1-{\displaystyle \frac{g_{m11}{r}_{o11}{r}_{o7}}{2g_{m1}{r}_{o1}{r}_{o5}}}),$$

(41)

where the equivalent resistance is $R_{out}\approx 0.5g_{m11}{r}_{o11}{r}_{o7}$

Using resistive voltage division, the Thevenin equivalent voltage is found to be $V_{out1}=b_4{V}_{dd}$

$$b_4\approx {\displaystyle \frac{1+\frac{g_{m3}}{g_{m9}}}{g_{m11}{r}_{o11}{g}_{m3}{r}_{o7}}},$$

(42)

The Thevenin equivalent voltage induced by $V_{in}$ is $-A{V}_{in}$:

$$A=g_{m1}(g_{m9}{r}_{o9}{r}_{o7}||g_{m11}{r}_{o11}{r}_{o7}),$$

(43)

Where $R=g_{m9}{r}_{o9}{r}_{o9}\left|\right|g_{m11}{r}_{o11}{r}_{o7}$ denotes the output resistance of the first stage. By writing the node current equation at node $V_o$ , the relationship between $V_{dd}$ and $V_o$ is obtained:

$$V_{dd}(b+Rs{C}_2)=V_o[(A+1)+Rs(C_1+C_2)],$$

(44)

Subsequently, the PSRR is calculated as

$${\displaystyle \frac{1}{|PSRR(s)|}}={\displaystyle \frac{1+\frac{g_{m3}}{g_{m9}}}{g_{m11}{r}_{o11}{g}_{m3}{r}_{o7}A}},$$

(45)

$$Z=-{\displaystyle \frac{1+g_{m9}}{g_{m11}{r}_{o11}{g}_{m3}{r}_{o7}R{C}_2}},$$

(46)

$$P=-{\displaystyle \frac{g_{m1}}{C_1+C_2}},$$

(47)

$C_1$ is the compensation capacitor and $C_2$ represents the parasitic capacitance. Since the op-amp’s input resistance R is very high, the zero is located near the origin, while the pole is far from the origin:

$$PGB=|Z\times PSRR|=-{\displaystyle \frac{1+\frac{g_{m3}}{g_{m9}}}{g_{m11}{r}_{o11}{g}_{m3}{r}_{o7}R{C}_2}}\times {\displaystyle \frac{g_{m11}{r}_{o11}{g}_{m3}{r}_{o7}A}{1+\frac{g_{m3}}{g_{m9}}}}={\displaystyle \frac{g_{m1}}{C_2}},$$

(48)

3. Results and Discussions

In this section, we will apply the proposed method to design a fully differential op amp with high PSRR. The circuit was designed using Cadence Virtuoso IC617 with a 180 nm CMOS process. We will first list the calculation process of several important indicators, and find the aspect ratio of each transistor through the constraints of multiple indicators. Then compare the simulation results with the calculation results to verify the accuracy of the PSRR calculation method

At the same time, we use the PGB formula to more intuitively know how to improve the PSRR of this complex circuit. We performed a simulation and verified the correctness of the PGB theory by comparing the PSRR before and after the modification.

At the end of this section, the simulation results of the circuit are given, and the expected indicators and the size of each transistor are given in a table at the end of the chapter for reference.

Figure 14. Circuit architecture.

Figure 14. Circuit architecture.

a)

Gain Expression

The transconductance of the input stage, G_m1, is given as:

$$G_{m1}=g_{m1},$$

(49)

The voltage gain is expressed as:

$$A_{v1}=-g_{m1}\{[g_{m7}{r}_{o7}(r_{o1}|\left|r_{o9a}\right||r_{o9b})]||(g_{m5}{r}_{o5}{r}_{o3})\},$$

(50)

$$A_{v2}=-G_{m2}{R}_{o2}=-g_{m13}(r_{o11}||r_{o13}),$$

(51)

$$A_{dm}=A_{v1}·A_{v2},$$

(52)

b)

Transfer Function Optimization

As illustrated in Figure 15, the feedforward stage introduces a zero-pole pair in the transfer function, compensating for the dominant pole. This minimizes phase lag and extends the high-frequency bandwidth. The transfer function is given by

$$A_v(s)={\displaystyle \frac{s[g_{mf1}(C_{o1}+C_C)-g_{m1}{C}_C]+g_{mf1}{g}_{o1}+g_{m1}{g}_{mL}}{s^2{d}_2+s{d}_1+d_0}},$$

(53)

Where:

$$d_2=C_{o1}{C}_C+C_{out}(C_{o1}+C_C))$$

$$d_1=g_{o1}{C}_{out}+g_{out}(C_{o1}+C_C)+(g_{o1}+g_{mL})C_C$$

$$d_0=g_{o1}{g}_{out}$$

$$g_{o1}={\displaystyle \frac{1}{R_{o1}}}$$

c)

PSRR

We calculate the PSRR using the method presented in Chapter II. Referring to Figure 10. in Chapter II, the first stage of op amps can be equivalent to $V_{out}=(b_3+m_1)V_{dd}+A{V}_{in}$, Where:

$$b_3\approx (1+{\displaystyle \frac{g_{m3}}{g_{m6}}}){\displaystyle \frac{1}{g_{m3}{r}_{o0}}},$$

(54)

$$m_1={\displaystyle \frac{g_{m3}{g}_{m11}{r}_{o7}(r_{o9a}||r_{o9b})}{g_{m3}{g}_{m11}{r}_{o7}(r_{o9a}||r_{o9b})}}=1,$$

(55)

Referring to the calculation in Figure 9., replace the original b with here and replace with the transfer function of PSRR that can be obtained directly

$${\displaystyle \frac{1}{PSRR(s)}}={\displaystyle \frac{V_o}{V_{dd}}},$$

(56)

Assuming $Z_1\ll Z_2$,$C_1\ll C_C$,$C_1=C_{gb14}+C_{db6}+C_{db8}$,$r_{o9}\text{'}=r_{o9a}\left|\right|r_{o9b}$,$C_{gd9}\text{'}=C_{gd9a}\left|\right|C_{gd9b}$

$${\displaystyle \frac{1}{|PSRR(s)|}}={\displaystyle \frac{\frac{1}{r_{o6}}+[1-(1+\frac{g_{m14}}{g_{m5}})\frac{g_{m14}{r}_{o14}}{g_{m3}{r}_{o14}}}{g_{m14}A+(\frac{1}{r_{o14}}+\frac{1}{r_{o12}})}}\approx {\displaystyle \frac{1-(1+\frac{g_{m3}}{g_{m5}})\frac{g_{m14}{r}_{o14}}{g_{m5}-g_{m3}{r}_{oo}}}{g_{m14}{r}_{o14}A}},$$

(57)

$$Z_1=-{\displaystyle \frac{\frac{1}{r_{o14}}+[1-(1+\frac{g_{m3}}{g_{m5}})\frac{g_{m14}{r}_{o14}}{g_{m3}{r}_{oo}}}{R(g_{m14}+\frac{1}{r_{o14}})(C_{gs14}+C_1+C_C)+(b_3{C}_C-g_{m14}R{C}_{gs14})}}\approx -{\displaystyle \frac{1-(1+\frac{g_{m3}}{g_m})\frac{g_{m14}{r}_{o14}}{g_{m3}{r}_{oo}}}{g_{m14}{r}_{o14}R(C_1+C_C)}},$$

(58)

$$Z_2=-{\displaystyle \frac{R(g_{m14}+\frac{1}{r_{o14}})(C_{gs14}+C_1+C_C)+(b_3{C}_C-g_{m14}R{C}_{gs14})}{R{C}_{gs14}{C}_C}}\approx -{\displaystyle \frac{g_{m14}R(C_1+C_C)}{R{C}_{gs14}{C}_C}}\approx -{\displaystyle \frac{g_{m14}}{C_{gs14}}}$$

(59)

If $P_1\ll P_2$,$C_1\ll C_C$,$C_L\ll C_C$:

$$P_1\approx {\displaystyle \frac{-[g_{m14}A+(\frac{1}{r_{o14}}+\frac{1}{r_{o9}\text{'}})]}{(g_{m14}-g_{m1})R{C}_C+R(\frac{1}{r_{o14}}+\frac{1}{r_{o9}\text{'}})(C_{gd14}+C_C)+(C_{gd9}\text{'}+C_L+C_C)}}\approx -{\displaystyle \frac{g_{m14}A}{(g_{m14}-g_{m1})R{C}_C}}\approx -{\displaystyle \frac{g_{m14}{g}_{m1}}{(g_{m14}-g_{m1})R{C}_C}}\approx -{\displaystyle \frac{g_{m1}}{C_C}}=\mathrm{GB}$$

(60)

$$P_2=-{\displaystyle \frac{g_{m6}}{C_{gs14}+C{}_L+(C_{gd9a}||C_{gd9b})}},$$

(61)

$${\displaystyle \frac{1}{PSRR(s)}}={\displaystyle \frac{1-(1+\frac{g_{m3}}{g_{m2}})\frac{g_{m14}{r}_{o14}}{g_{m3}{r}_{o0}}}{g_{m14}{r}_{o14}A}}\times {\displaystyle \frac{(1+\frac{g_{m14}{r}_{o14}(C_1+C_C)s}{g_{m6}{r}_{o6}})(1+\frac{C_{gs14}}{g_{m14}}s)}{(1+\frac{s}{GB})(1+\frac{C_{gs14}+C_1+C_C}{g_{m14}}s)}},$$

(62)

$$PGB=|Z_1\times PSRR|=|{\displaystyle \frac{1-(1+\frac{g_{m3}}{g_{m5}})\frac{g_{m14}{r}_{o14}}{g_{m5}}}{g_{m14}{r}_{o14}R(C_1+C_C)}}\times {\displaystyle \frac{g_{m14}{r}_{o14}A}{1-(1+\frac{g_{m3}}{g_{m5}})\frac{g_{m14}{r}_{o14}}{g_{m3}{r}_{o0}}}}|={\displaystyle \frac{g_{m1}}{C_1+C_C}},$$

(63)

Constrained by the above formula, we calculated the initial dimensions by hand, and after several simulation adjustments, we determined the final dimensions of each transistor. Table 1 shows the design specifications of this circuit.

The PSR is defined as the ratio of output voltage change to the power supply perturbation, representing how strongly supply disturbances couple directly into the output. In contrast, the PSRR is commonly defined as the inverse of this ratio or equivalently as the difference between the amplifier's gain and PSR, namely:

$$PSRR=Gain-PSR$$

In practical industry designs, PSR is typically of direct concern because it quantifies the amount of power-supply noise propagating into the signal path. However, directly analyzing and optimizing PSR is complicated due to intricate interactions among circuit parameters and the resulting mathematical complexity. Conversely, analyzing both PSR and PSRR—especially using our proposed PGB methodology—are significantly more straightforward and intuitive. By utilizing the PGB framework, we know that we can enhance the performance of PSRR by increasing g_m or reducing C_c according to (63). The simulation results before and after the modification are shown below:

Figure 16. Gain simulation experiment.

Figure 16. Gain simulation experiment.

As illustrated in Figure 17 and Figure 18, by optimizing these parameters through the intuitive guidance provided by PGB, we achieve enhanced PSRR performance. Due to the explicit mathematical relationship between PSRR and PSR, improvements in PSRR obtained via the PGB approach can indirectly yet effectively inform designers how to optimize PSR performance. This demonstrates the practical advantage of using the PGB metric as an intuitive design tool, bridging the gap between complex PSR calculations commonly faced in industrial practice and straightforward PSRR optimizations.

We also performed some other simulations on the circuit. Figure 19 shows the basic indicators of the circuit at different process corners, and Figure 19-d shows the PSRR of the circuit at each process corner after PGB operation adjustment

The PSRR of this circuit is more than 155dB at 100kHz for all process conners. It is also very good at high frequencies. We also tested the PSRR and PSR performance of the circuit under different temperature conditions, as shown in Figure 20. And the results of Monte Carlo simulation are shown in the Figure 21.

Table 2 shows the simulation results of this circuit and the comparison with other high PSRR op amps. Table 3 shows the final dimensions of each transistor after re-adjustment according to the PGB method. The design requirements are achieved in all indicators and a good FOM value is achieved. The PSRR calculation method proposed in this article provides a new idea for future circuit design, and the PGB optimization method can also simplify the complex process of PSR calculation.

4. Conclusion

Experimental validation in Section III demonstrates that by leveraging Thevenin’s equivalence principle, the proposed method transforms multi-stage op-amps into simplified black-box models, significantly reducing computational complexity while enhancing intuitive analysis. The introduced PGB metric, which correlates the DC PSRR value with the first dominant pole frequency, eliminates the reliance on exhaustive S-parameter modeling. This enables a computationally efficient evaluation of PSRR performance within the target frequency band. While the PGB framework assumes validity primarily below the GBW—a constraint inherent to its first-order approximation—it remains highly practical for industrial design scenarios where critical PSRR specifications typically reside in low-to-mid frequency ranges. the PGB metric provides actionable insights for optimizing PSRR through parameter adjustments and facilitates rapid comparative analysis of competing circuit topologies.

The proposed framework not only simplifies PSRR analysis for asymmetric and multi-stage circuits but also provides actionable insights for optimizing key parameters (e.g., transconductance, compensation capacitance) to meet stringent industrial requirements. Future work will extend this approach to mixed-signal systems and explore its integration with machine learning-driven design automation tools.