Design Analysis of a Modified Current Reuse Low Power Wideband Single-Ended CMOS LNA

1. Introduction

Wideband low-noise amplifiers (LNAs) cover more wireless communication and should amplify with a flat response the weak signal received by the antenna with minimal noise injection. Input impedance matching and linearity with flat response are also two important parameters of a wideband LNA to prevent signal reflections and produce harmonic distortion whole bandwidth [1]. There is a trade-off between mentioned parameters with power consumption [2]. These days the low power designs have received a lot of attention, as most of systems are powered by only a single lithium battery which must work for several days (mobile phone) or even a year (medical devices) that is why designing low-power circuits has become a major challenge for RF designers [3]. LNAs can be designed in two modes of single-ended and differential. Although single-ended LNAs have lower gain and linearity, they are designed easily with good stability and low-noise performance whereas differential LNAs are excellent to achieve high gain and better linearity [4]. Common gate (CG) and common source (CS) circuits are used individually or a combination of both in differential and single-ended LNAs [5]. Although CG topology shows the best performance for a wideband LNA because of the low input impedance of independent of frequency, it needs high power to satisfy input impedance matching and NF, that is why it is not used alone for low power circuits. The CS with shunt feedback is another choice to design a wideband LNA which needs to consume high power to achieve high gain and low NF, that is why it is often used with current reuse technique [6].

The noise cancellation technique is another method for reducing thermal noise with low power consumption which was reported in 2004 [7]. Figure 1a shows conventional current reuse with shunt feedback [2] and Figure 1b noise cancellation LNA [7]. In [9] by using CS and CG a differential LNA has been reported which by using a cross-couple amplifier structure between positive and negative outputs linearity has been improved whole band width without decreasing gain. Although the reported results are excellent, an external RF chock has been used, power consumption is around 12 mW and it is also required a buffer circuit to measure. Authors in [10] has reported a differential LNA by combination of CG and CS in 65 nm CMOS. Although they have obtained high gain, the reported circuit consume 19.8 mW that is very high for low power devices, also the circuit needs an external RF chock. Reference of [11] has presented a differential LNA by using CG and CS. The reported results are reasonable with a 5.7 mw power that cover frequency range of 0.05 to 1.3 GHz; however, an external RF chock has been used. In [12] a differential LNA for sub-GHz applications has been provided which by using a CG and current reuse positive and negative outputs has been formed, respectively. Although the reported power is 3 mW, minimum NF is 3.6 dB that may not be acceptable for some sensitive applications. Kishore and Venkataramani in [13] has presented an inductor less wideband LNA that cover 0.18 to 2 GHz. The presented circuit has used combination of CG and CS, transconductance (gm) is also boosted by using a cross-couple structure between differential nodes. The results were reported in an unmatched output impedance condition, if the buffer current is calculated, the results will become poor. In [14] a shunt-feedback and feedforward technique has been used to design a single-ended wideband LNA which it cancels out noise and distortion simultaneously with ultra-low power of under 1 mW. Although the reported circuit consumes ultra-low power, it needs buffer network to measure and minimum NF of 4.45 dB has been reported which may not be suitable for some applications which need high sensitivity. Yunyou Pu and Wei Li have reported a differential wideband LNA from 0.2 to 3.2 GHz by using CS and CG and noise cancellation technique [15]. Although they have achieved to high gain and minimum NF of 1.4 dB, power dissipation is 17.4 mW that is very high for low power applications. Reference of [16] has presented a single-ended LNA by combination CG, current reuse and noise cancellation circuits for low voltage and low power applications. Although the reported results are acceptable, the area and power of buffer circuit has not been calculated. In [17] a differential wideband LNA by using noise and distortion cancellation technique with 1.6 GHz bandwidth has been provided. The minimum NF of 1.1 dB has been reported, however the power consumption is little high 9.1 mW that is not reasonable for low power systems.

This paper presents a single-ended wideband LNA for low-power applications with an operating frequency in the range of 0.17 to 2.68 GHz. The proposed circuit consists of two stages, a current reuse with shunt feedback and a series inductor peaking technique in the first stage, and a CG and CS form second stage. Both stages consume the same DC current which are isolated from each other by using large metal-insulator-metal capacitor (MIMCAP). By this method power consumption is reduced significantly. Output impedance is also matched to 50 Ω load which does not require an extra buffer network for measurement. The paper is organized as follows. Section 2 analyze the proposed LNA structure in details. Section 3 presents the post-layout simulation results and finally, Section 4 provides the conclusion.

2. Analysis of the Proposed LNA

The proposed wideband LNA with value of elements is shown in Figure 2. The proposed LNA consists of two stages. Transistors of M₁, M₂ form first stage as a current reuse circuit which DC point in A node is set by a common mode feedback (CMFB) circuit. The length of transistors M₁ and M₂ is chosen to be slightly longer than the minimum length of the technology used (60 nm) to increase the intrinsic impedance between source and drain (1/gds), which slightly increases the voltage gain at node A [8]. M₁, M₂ also act as a gm boosting for M₅, as a result the signal of A node with again amplification appears in B node. DC point of B node is also set by CMFB2. M₈ acts as a shunt- series feedback to meet a wideband input impedance matching and also linearity improvement, this transistor is biased in sub-threshold region to decrease power, besides because gain in B node is high, input impedance matching is satisfied very well without increasing the feedback network coefficient (gm₈). Transistors of M₃ and M₄ form second stage of the proposed LNA which consumes the same DC current as first stage and are isolated from first stage by capacitor of C_B1. M₃, M₄ act as a buffer stage which are used for output impedance matching. Gate terminal of the M₄ is also connected to input (node of C) and acts as noise and distortion cancellation technique to improve slightly gain, NF linearity. It means that the noise and harmonic distortion returned by the feedback network is slightly amplified by this transistor with a 180˚ phase difference and summed with the output, which reduces distortion and noise.

Inductor Lg is used to help flat gain, input impedance matching and slightly bandwidth. The details of the input impedance matching, voltage gain, NF, and linearity of the proposed balun-LNA are presented in the following.

2.1. Input Impedance Matching

Figure 3 shows the small-signal model of input of the proposed wideband LNA to calculate the input impedance. The inductor Lg more or less compensates parasitic capacitors (C_P) for frequencies of above 1.5 GHz to satisfy input impedance matching whole desired bandwidth (0.17 to 2.68 GHz).

According to the Figure 3, the input impedance of the proposed LNA is approximately calculated as follows:

$$Zin\approx {\displaystyle \frac{1}{S{C}_1}}‖\hspace{0.17em}\hspace{0.17em}\left({\displaystyle \frac{S^{2}Lg{C}_P+1}{S{C}_P+g{m}_8{Z}_B\left(S^{2}Lg{C}_P+1\right)\times \left(\frac{g{m}_6}{1+g{m}_{6}r{o}_7}+\frac{g{m}_5}{S^{2}Lg{C}_P+1}-\frac{g{m}_5{Z}_A\left(g{m}_5-\left(g{m}_1+g{m}_2\right)\right)}{\left(1+g{m}_5{Z}_A\right)\left(S^{2}Lg{C}_P+1\right)}+1\right)}}\right)$$

(1)

where $Z_A\approx r{o}_1‖r{o}_2$ , $Z_B\approx \left(g{m}_{6}r{o}_{6}r{o}_7\right)‖\left(g{m}_{5}r{o}_5\left(r{o}_1‖r{o}_2\right)\right)$ and C_P is parasitic capacitors of D node that approximately equals:

$$C_P\approx \left(Cg{s}_1+Cg{s}_2\right)+\left(Cg{d}_1+Cg{d}_2+Cg{s}_5\right)\left(1+\left(g{m}_1+g{m}_2\right)\left(r{o}_1‖r{o}_2\right)\right)$$

(2)

Based on the Equation (1), when Lg and C_P are resonated, the input impedance tends towards zero which causes S₁₁ to be spoiled, however the amount of the resonance frequency is around 6 GHz that is much more than desired bandwidth (0.17 - 2.68 GHz).

2.2. Voltage Gain

Figure 4 shows AC model of the proposed circuit. As is clear, first stage is formed by M₁, M₂ M₅, M₆ and feedback of M₈. Transistors M₃ and M₄ form second stage.

By considering an output load of R_L of 50 Ω, voltage gain can be approximately calculated as follows:

$${\displaystyle \frac{V_O}{V_S}}\approx {\displaystyle \frac{\left(g{m}_3{Z}_B\left(1+g{m}_{6}r{o}_7\right)\left(-\left(g{m}_1+g{m}_2\right)\left(1+g{m}_{6}r{o}_7\right)-g{m}_6\right)-g{m}_4\left(1+g{m}_{6}r{o}_7\right)\right)R_L}{\left(1+g{m}_3{R}_L\right)\left(1+g{m}_{6}r{o}_7\right)\left(1+g{m}_8{R}_S\left(\left(g{m}_1+g{m}_2\right)Z_B+1\right)\right)+g{m}_8{R}_{S}g{m}_6{Z}_B}}$$

(3)

where $Z_B\approx \left(g{m}_{6}r{o}_{6}r{o}_7\right)‖\left(g{m}_{5}r{o}_5\left(r{o}_1‖r{o}_2\right)\right)$ . Inductor Lg and parasitic capacitors are not considered in Equation (3) to simplify calculation and better understanding, however the effect of Lg on the gain is explained below.

The inductor Lg acts as a series inductive peaking to compensate parasitic capacitors of D node. Figure 5 shows effect of Lg on the gain, as shown, it is clear that before the current reuse stage, a passive gain is created by the inductor Lg at D node, which contributes to increase the 3_dB bandwidth.

2.3. Noise Analysis

Considering the proposed circuit consists of two stages, according to the Friis equation, it is clear that the first stage has the main effect on NF [2]. Although M₄ is connected between the input and output as a CS and can play the role of noise cancellation technique [7], the conditions for complete cancellation cannot be met due to the low-power design and also the connection of a 50 Ω load to the output. In other words, the noise sampling coefficient by the M₈ feedback is much lower than its amplification by M₄ with R_L of 50 Ω that is why it has low effect on NF improvement. In first stage, thermal noise of M₅ and M₆ can be ignored because they have a degenerated impedance in their source terminals [2]. Transistor M₈ is biased in sub-threshold region and low current by a large resistor of R₁ to decrease power dissipation, although shot noise is comparable to thermal noise in this regime [18], as a result it can also be ignored because seen impedance in this node (node of C) is too small by around Rs. As a result, main noise depends on current reuse stage, so NF is calculated as following:

$$NF=1+{\displaystyle \frac{{\left(r{o}_1‖r{o}_2\right)}^2{\left(1+gm{}_{8}Rs\right)}^2\gamma \left(g{m}_1+g{m}_2\right)}{{\left(1+\left(g{m}_1+g{m}_2\right)\left(r{o}_1‖ro{}_2\right)\right)}^{2}Rs}}$$

(4)

where γ is the correction factor which is assumed to be the same for NMOS (M₁) and PMOS (M₂) for simplicity. According to Equation (4), because the value of $\left(g{m}_1+g{m}_2\right)\left(r{o}_1‖ro{}_2\right)$ is much higher than one, the (4) is simplified to (5).

$$NF\approx 1+{\displaystyle \frac{{\left(1+gm{}_{8}Rs\right)}^2\gamma }{\left(g{m}_1+g{m}_2\right)Rs}}$$

(5)

According to Equation (5), obviously, the greater the effect of the feedback network of M₈ $\left(g{m}_8{R}_S\right)$, the worse the NF will be.

2.4. Linearity Analysis

Usually, both types of LNAs (single-ended and differential) are designed in one stage to achieve good linearity [2]. In a non-ideal amplifier signal is approximately amplified as [2]:

$$y\left(t\right)\approx {\alpha }_{1}x\left(t\right)+{\alpha }_2{x}^2\left(t\right)+{\alpha }_3{x}^3\left(t\right)+\mathrm{...}$$

(6)

where α₁ is as the small-signal gain. In differential LNAs due to the output differential signal, second term of (6) can be decreased significantly [2], but third order harmonic is still problematic [9].

Figure 6 illustrates the mechanism of linearity improvement of the proposed circuit. If two interferer signals of ${\omega }_1,\hspace{0.17em}\hspace{0.17em}{\omega }_2$ is applied to input, a third order harmonic of $2{\omega }_2-{\omega }_1$ and $2{\omega }_1-{\omega }_2$ is produced in output of first stage of current reuse (A node). The produced harmonic node of A comes to node of B through M₅ and is also brought to input (node of C) through feedback of M₈ then it is amplified with 180˚ phase different by M₄ that can decrease the distortion of output and improve linearity [7]. Based on the Figure 6, in the proposed circuit the conditions for complete harmonic cancellation are not provided, because the harmonic appeared in node B reaches node C with a large attenuation coefficient which transistor M₄ cannot fully compensate this attenuation in output due to low power design and consequently low gm₄, which is why linearity of the proposed LNA is improved by slightly less than 2 dB.

3. Simulation Results

The proposed low power single-ended wideband LNA is suitable for low power Mult-standards receivers which cover the frequency range of 0.17-2.68 GHz such as (GSM, WLAN and Bluetooth). The proposed LNA is designed in 65 nm CMOS technology with 1 V supply voltage and a reference current (IREF) of 50µA for bias network to improve circuit stabilization under process, supply and temperature (PVT) variations. Figure 7 shows the layout of the proposed LNA with a core area of 0.45 mm². The results of the proposed wideband LNA across PVT and corner variations are presented in Figure 8 and Figure 9, respectively. As shown, S₁₁ and S₂₂ have a value of less than -10 dB over the entire desired bandwidth, also the power gain (S₂₁) and NF have an amount of more than 15 dB and less than 3.24 dB over the desired bandwidth, respectively. Figure 10 shows stability factor (Kf) that has an amount of more than 1 from 0.1 to 12 GHz which means the proposed circuit is unconditionally stable.

To ensure the value of the inductance and quality factor (Q) of the Lg, electromagnetic (EM) simulation has been performed. Figure 11 and Figure 12a demonstrate substrate stack map of 65 nm CMOS technology and inductor Lg for EM simulation. Figure 12b illustrates EM simulation of Lg which values of inductance and Q-Factor at 2 GHz are obtained 5.9 nH and 13.9, respectively. The Self-resonant frequency (SRF) is also around 9 GHz that is a reasonable value for the desired bandwidth (0.17 to 2.68 GHz).

As mentioned in the linearity analysis section, M₄ improves linearity. To prove it, IIP3 is simulated in two cases that is shown in Figure 13a,b. Once when the terminal gate of M₄ is connected to the input and M₄ acts as a CS which the mechanism of distortion improvement is carried out and once when M₄ acts only as a current source for second stage. Figure 14a,b show intercept point three (IIP3) at 2.4 GHz and IIP3 versus input frequency, respectively. As shown in Figure 14a, by simulation of two-tone tests with 10 MHz spacing at 2.4 GHz when M₄ is as CS, an IIP3 of -14.9 dBm is achieved. Figure 15b, shows both curves of IIP3 at entire desired bandwidth when M₄ acts as CS and current source, respectively. As shown the IIP3 is improved when M₄ acts as a CS. Table 1 summarizes the results of the proposed wideband LNA in different corners and temperatures. Although the proposed LNA show a small variation in different corners, it is robust against corner and temperature variations. Table 2 represents a comparison to state-of-the art work between the proposed LNA and some similar recent works. Figer of merit (FoM) are calculated as follow [16]:

$$FOM=20{\log }_{10}\left({\displaystyle \frac{S_{21}[abs]\hspace{0.17em}\hspace{0.17em}.\hspace{0.17em}\hspace{0.17em}B{W}_{-3dB}[GHz]}{P_{DC}[mW]\hspace{0.17em}\hspace{0.17em}.\hspace{0.17em}\hspace{0.17em}(F_{\min }-1)}}\right)$$

(7)

Excluding [15] which has a fully output impedance matching, other cited references only have reported the LNA core power, that is why some of them has a FoM of higher than the proposed circuit. Only [12] has mentioned the output buffer power of 9 mW, which would make its FoM much lower if it were included. The results of the proposed LNA are reported without using extra output buffer and under conditions of fully output impedance matching. One of the advantages of the proposed topology used is to perform output impedance matching without high power consumption.

4. Conclusions

In this paper, a low power wideband single-ended LNA is analyzed and presented which cover 0.17 to 2.68 GHz and is suitable for low power multi-standards wireless applications. By using two stages of amplifier with same DC current and noise and distortion cancellation method all parameters of a wideband LNA have been satisfied plus output impedance matching in a low power design. One of the advantages of the proposed LNA is a fully output impedance matching with low power consumption so no additional buffer is required for measurement.