Black-Box Modeling Approach with PGB Metric for High-Frequency PSRR Prediction in Op-Amps

1. Introduction

The swift advancement of electronic technology has given rise to the necessity for low-power and high-performance circuit design [1,2,3,4]. In this context, fundamental building blocks of any chip, such as operational amplifiers, low-dropout regulators (LDOs), and bandgap references, have become increasingly important. Maintaining circuit stability under diverse operating conditions thus becomes critical. The PSRR serves as a key metric for assessing a circuit’s ability to suppress power supply noise, directly impacting signal integrity and system stability. In the realm of high-precision medical devices [5], enhancing the PSRR augments measurement precision and diagnostic reliability. In high-speed communication systems, it attenuates noise interference during data transmission. And in portable devices, it prolongs battery life and enhances immunity to interference.

Conventional PSRR calculation methods rely predominantly on simplified analyses of system poles and zeros, often using low-frequency equivalent circuit models. However, as circuits operate at higher frequencies, parasitic capacitance, inductance, and other high-frequency effects introduce significant deviations between calculated and actual performance. This discrepancy becomes even more pronounced in radio frequency (RF) and high-speed communication circuits, where complex interactions between power supply noise and parasitic parameters exacerbate the issue. Moreover, existing methods lack a unified theoretical framework and standardized calculation process, forcing designers to invest substantial time in theoretical derivation and experimental validation when addressing novel circuit architectures. Such constraints hinder design efficiency and innovation.

To overcome these challenges, we propose a novel PSRR calculation theory. Our approach evaluates the PSRR of a two-stage operational amplifier by modeling the first stage as a black box with defined input and output. We apply the Thevenin equivalent model to capture the internal behavior of the first stage and reintegrate this result into the overall circuit model. This strategy simplifies the calculation and enhances its intuitiveness. In addition, the proposed theory offers a detailed description of key parameters—including poles, zeros, and gain bandwidth.

Furthermore, industrial design pays more attention to the analysis of power supply rejection ratio (PSR). Since it involves complex S-parameter models, it is difficult to optimize it directly. This paper proposes a simplified evaluation method based on PGB, which avoids the tedious S-parameter calculation by directly extracting PSRR and first-order pole characteristics, thereby achieving efficient and intuitive PSR performance prediction within the target frequency band. This method shows universality before the gain-bandwidth product (GBW), and can uniformly explain the phenomenon that different circuit architectures (such as LDO) have differentiated UGB-level PSR characteristics under the same low-frequency PSR and pole configuration.

We validate the proposed method by analyzing typical circuit structures. The rest of this paper is organized as follows. Section II reviews the traditional PSRR calculation methods and introduces the theoretical basis of our method and details the PSRR calculation process and zero-pole characteristics of different circuits. Section III verifies the accuracy of PSRR calculation through the design and simulation of complex circuits and confirms the feasibility of optimizing PSRR through PGB calculation analysis. Finally, Section IV summarizes the advantages of the proposed method and outlines the direction of future research.

2. Materials and Methods

2.1. Related Work

Razavi introduced a small-signal model–based method for PSRR calculation [6]. This approach works well for simple and symmetric circuits by directly computing PSRR through the analysis of small-signal gain:

$$\mathit{PSRR}=\frac{A_{dm}}{A},$$

(1)

where A_dm denotes the differential gain and A represents the overall gain of the small-signal model.

However, as circuit designs become more complex, especially with asymmetric or multistage circuits, the limitations of this method become evident. The extended method proposed by Grey [7] is theoretically more complete but suffers from cumbersome calculation procedures and unvalidated suitability for high-frequency circuits.

PSRR computation is influenced by the characteristics of the input, intermediate, and output stages of a two-stage operational amplifier. For instance, the bias current, input impedance, and offset voltage at the input stage significantly affect PSRR; circuits designed with low bias current and high input impedance tend to exhibit improved PSRR. In the intermediate stage, higher gain amplifies power supply noise, thereby reducing PSRR. Similarly, the output stage must be designed to balance driving capability with noise suppression to maintain a high PSRR.

To tackle the challenges associated with complex circuit analysis, we leverage Allen's interpretation of PSRR [8] and develop a "black-box" model that simplifies the intricate circuitry. This model is particularly applicable to Thevenin Equivalent Circuit Analysis, where the Thevenin theorem simplifies linear resistor networks with independent sources into a single voltage source in series with a resistance. Specifically, for any single-port network N, the port can be represented equivalently by a voltage source —whose value corresponds to the open-circuit voltage (V_o)—in series with a resistance R_o, which is the equivalent resistance observed at the port when all independent sources are deactivated.

Figure 1. Thevenin equivalent circuit.

Figure 1. Thevenin equivalent circuit.

2.2. Proposed Methodology

In this section, we employ the black-box theory proposed in the previous chapter to analyze the PSRR of various operational amplifiers.

2.2.1. PSRR Calculation for P-Input Two-Stage Op-Amps

Figure 2. Typical structure of a P-input two-stage op-amp.

Figure 2. Typical structure of a P-input two-stage op-amp.

In this op-amp, the input stage usually consists of two P-type MOSFETs (M₁ and M₂) that receive the input signal and provide initial amplification. Transistors M₃ and M₄ act as load devices and work in conjunction with M₁ and M₂ to enhance the gain of the input stage. Current mirrors comprising M₅ and M₇ supply a stable bias current to the input stage while ensuring that the currents in M₁ and M₂ are matched. In the output stage, transistor M₆ further amplifies the signal from the input stage and provides sufficient drive capability for the load.

To simplify the calculation, we treat the first stage of the op-amp as a “black box” with input terminals which denoted as $V_{in}$ and an output terminal which denoted as $V_{out}$. This is illustrated in Figure 3.

The processing of the first stage is performed in several steps:

(a)

Evaluating the Impact of V_dd on the Thevenin Equivalent Output Voltage of the First Stage

Figure 4. Thevenin equivalent circuit for the first stage of the op-amp.

Figure 4. Thevenin equivalent circuit for the first stage of the op-amp.

The first stage is viewed as an independent module. Based on the Thevenin theorem, the equivalent voltage generated by $V_{dd}$ is given by $V_{out1}=b_1{V}_{dd}$.

$$b_1\approx {\displaystyle \frac{1}{2g_{m3}{r}_{o5}}},$$

(2)

• (b) Evaluating the Impact of Vin on the Thevenin Equivalent Output Voltage of the First Stage

Figure 5. Thevenin equivalent output voltage of the first stage.

Figure 5. Thevenin equivalent output voltage of the first stage.

For a differential input $V_{in}$ , the corresponding Thevenin equivalent output voltage is:

$$\mathrm{A}={\mathrm{g}}_{m1}(r_{o2}||r_{o4}),$$

(3)

Likewise, for a common-mode input $V_{in}$, the corresponding Thevenin equivalent output voltage is:

$$V_{th}=-{\displaystyle \frac{V_{in}}{\frac{g_{m3}}{g_{m1}}+2g_{m3}{r}_{o5}}},$$

(4)

The common-mode output voltage is relatively small and can be combined with the differential output voltage. Therefore, in the subsequent calculations, the common-mode contribution is typically neglected.

• (c) Constructing the Thevenin Equivalent Circuit

Using the superposition theorem, the first stage is further simplified to a structure consisting of a voltage source and a resistor, as shown in the lower left area of Figure 6, where $R=r_{o2}\left|\right|r_{o4}$ represents the output resistance of the first stage.

(a)

Deriving the PSRR Transfer Function

The equivalent circuit for the two-stage op-amp is shown in Figure 7. Considering the gate-drain capacitance C_gd of M₇, we use small-signal analysis to write the node current equations and thereby solve for the PSRR transfer function.

First, we write the node current equation at node $V_1$:

$${\displaystyle \frac{(b_1{V}_{dd}+A{V}_o)-V_1}{R}}+s(V_o-V_1)C_c=V_{1}s{C}_1,$$

(5)

$$V_1={\displaystyle \frac{b{V}_{dd}+(A+Rs{C}_c)V_o}{1+Rs(C_1+C_C)}},$$

(6)

Similarly, writing the node current equation at node $V_o$:

$$(V_o-V_1)s{C}_C+g_{m6}{V}_1+{\displaystyle \frac{V_o}{r_{o6}}}+V_{o}s{C}_L={\displaystyle \frac{V_{dd}-V_o}{r_{o7}}}+(V_{dd}-V_o)s{C}_{gd7},$$

(7)

$$V_1={\displaystyle \frac{V_{dd}（\frac{1}{r_{o7}}+\mathrm{s}{C}_{gd7}）-V_o[(\frac{1}{r_{o7}}+\frac{1}{r_{o6}})+s(C_c+C_L+C_{gd7})]}{g_{m6}-s{C}_C}},$$

(8)

By equating (5) and (7):

$$V_1={\displaystyle \frac{V_{dd}（\frac{1}{r_{o7}}+\mathrm{s}{C}_{gd7}）-V_o[(\frac{1}{r_{o7}}+\frac{1}{r_{o6}})+s(C_c+C_L+C_{gd7})]}{g_{m6}-s{C}_C}}={\displaystyle \frac{b{V}_{dd}+(A+Rs{C}_c)V_o}{1+Rs(C_1+C_C)}},$$

(9)

$${\displaystyle \frac{1}{PSRR(s)}}={\displaystyle \frac{V_o}{V_{dd}}},$$

(10)

In the derivation above, it is assumed that $L_5=L_7$, due to matching requirements. if we set ${({\displaystyle \frac{W}{L}})}_7=M{({\displaystyle \frac{W}{L}})}_5$ and ${({\displaystyle \frac{W}{L}})}_6=N{({\displaystyle \frac{W}{L}})}_3$,we obtain that $I_7=M{I}_5$, $r_{o5}=M{r}_{o7}$, and:

$${\displaystyle \frac{g_{m6}{r}_{o7}}{2g_{m3}{r}_{o5}}}={\displaystyle \frac{1}{2M}}\sqrt{{\displaystyle \frac{K_n^{\text{'}}{(\frac{W}{L})}_6{I}_6}{K_n^{\text{'}}{(\frac{W}{L})}_3{I}_3}}}={\displaystyle \frac{1}{2M}}\sqrt{{\displaystyle \frac{{(\frac{W}{L})}_6}{{(\frac{W}{L})}_3}}\times 2M}=\sqrt{{\displaystyle \frac{N}{2M}}},$$

(11)

Next, we derive the DC PSRR value as well as the positions of the zero and pole:

$${\displaystyle \frac{1}{|PSRR(s)|}}={\displaystyle \frac{\frac{1}{r_{o7}}(1-\sqrt{\frac{N}{2M}})}{g_{m6}A+(\frac{1}{r_{o7}}+\frac{1}{r_{o6}})}}\approx {\displaystyle \frac{1-\sqrt{\frac{N}{2M}}}{A{g}_{m6}{r}_{o7}}},$$

(12)

Assuming $Z_1\ll Z_2,C_{\mathit{gd}7}\ll C_{\mathrm{C}},C_1\ll C_{\mathrm{C}}$, and for stability, we have $g_{m1}\ll g_{m6}$:

$$Z_1\approx -{\displaystyle \frac{\frac{1}{r_{o7}}(1-\sqrt{\frac{N}{2M}})}{\frac{R}{r_{o7}}(C_1+C_C)+C_{gd7}+b_1{C}_C}}\approx -{\displaystyle \frac{1-\sqrt{\frac{N}{2M}}}{R(C_1+C_C)+r_{o7}{C}_{gd7}}}\approx -{\displaystyle \frac{1-\sqrt{\frac{N}{2M}}}{R(C_1+C_C)}},$$

(13)

$$\begin{array}{l}{Z}_2\approx -{\displaystyle \frac{\frac{R}{r_{o7}}(C_1+C_C)+C_{gd7}+b_1{C}_C}{R{C}_{gd7}(C_1+C_C)}}\approx -{\displaystyle \frac{R(C_1+C_C)+r_{o7}{C}_{gd7}}{r_{o7}R{C}_{gd7}(C_1+C_C)}}\approx -{\displaystyle \frac{1}{r_{o7}{C}_{gd7}}}\\ \end{array},$$

(14)

Further assuming $P_1\ll P_2$, leads to:

$$\begin{array}{c}{P}_1\approx {\displaystyle \frac{-[g_{m6}A+(\frac{1}{r_{o6}}+\frac{1}{r_{o7}})]}{(g_{m6}-g_{m1})R{C}_C+R(\frac{1}{r_{o6}}+\frac{1}{r_{o7}})(C_1+C_C)+(C_{gd7}+C_L+C_C)}}\approx -{\displaystyle \frac{g_{m6}A}{(g_{m6}-g_{m1})R{C}_C}}\approx -{\displaystyle \frac{g_{m6}{g}_{m1}}{(g_{m6}-g_{m1})R{C}_C}}\approx -{\displaystyle \frac{g_{m1}}{C_C}}=\mathrm{GB}\\ \end{array}$$

(15)

$$P_2={\displaystyle \frac{g_{m6}}{C_1+C{}_L+C_{gd7}}},$$

(16)

$${\displaystyle \frac{1}{|PSRR(s)|}}={\displaystyle \frac{1-\sqrt{\frac{N}{2M}}}{A{g}_{m6}{r}_{o7}}}\times {\displaystyle \frac{(1+\frac{Rs(C_1+C_C)}{1-\sqrt{\frac{N}{2M}}})(1+r_{o7}{C}_{gd7})}{(1+\frac{s}{GB})(1+s\frac{C_1+C{}_L+C_{gd7}}{g_{m6}})}},$$

(17)

The location of $Z_1$ is the closest to the origin relative to the first pole. Whether the DC PSRR value is positive or negative depends on the specific values of N and M When N is approximately twice that of M, the DC PSRR value becomes very high; however, the zero also shifts closer to the origin.

The PSRR is influenced by two signal paths within the op-amp. In the first path, the signal entering from $r_{o5}$ reduces the output voltage at low frequencies; in the second path, the signal entering from $r_{o7}$ has the opposite effect and increases the output voltage. For simplification, the drain of M₅ is grounded, thereby neglecting the signal contribution from M₅ and resulting in a positive DC PSRR gain. Under ideal bias current source conditions, if N is greater than twice that of M, the PSRR is negative; if N is less than twice that of M, the PSRR is positive. The location of the zero is also closely related to the ratio of these two parameters.

PGB (PSR Gain Bandwidth):

By approximating the PSRR curve as having a single zero, and drawing an analogy with the gain-bandwidth product in op-amps, we define PGB as the product of the zero frequency and the DC PSRR value:

$$\begin{array}{c}PGB=|Z_1\times PSRR|=|-{\displaystyle \frac{1-\sqrt{\frac{N}{2M}}}{R(C_1+C_C)}}\times {\displaystyle \frac{A{g}_{m6}{r}_{o7}}{1-\sqrt{\frac{N}{2M}}}}|={\displaystyle \frac{g_{m1}{g}_{m6}{r}_{o7}}{C_1+C_C}}\\ \end{array},$$

(18)

According to (18), when the PGB value is large, the −20 dB/dec asymptote of the main zero shifts further away from the origin while maintaining its slope, thereby improving the frequency characteristics in the BE segment. If, while keeping other parameters constant, a parameter is adjusted so that it approaches 2M, the DC PSRR value increases significantly and the zero moves toward the origin, optimizing the frequency response in the C_L segment. If the frequency of interest falls on the DE segment of the curve, the impact of the parameter change is relatively small. As shown in Figure 8, curve CDE represents the original PSRR response, while curve ABE corresponds to the frequency response after a parameter adjustment.

This process bears some similarity to considerations of the loop bandwidth (GB) of the two-stage op-amp. Increasing a particular parameter directly enhances the DC PSRR value, which is beneficial for our analysis. Under stability constraints, reducing the parameter C_c shifts ${\omega }_{-3dB}$ outward, thereby improving the frequency response; similarly, increasing $g_{m6}$ shifts the BE line outward; increasing $r_{o5}$ and $r_{o7}$ directly optimizes the DC PSRR value; while increasing $r_{o2}$ and $r_{o4}$ raises the DC PSRR value but also moves${\omega }_{-3dB}$ closer to the origin, benefiting only the low-frequency response—the PGB remains unchanged, and hence the improvement for high frequencies is limited. However, since the bandwidth that the industry is concerned about is usually low-frequency, PGB can play a vital role in the design of specific field.

2.2.1. PSRR Calculation for N-Input Two-Stage Op-Amps

In this subsection, we adopt a similar analytical approach to study the PSRR of N-input two-stage op-amps and thereby demonstrate the portability of the new PSRR calculation theory.

Based on the analysis in Section A for a typical P-input two-stage op-amp, we consolidate the simplified flowchart for a common N-input two-stage op-amp into a single diagram, as shown in Figure 9.

The following quantities are computed: the Thevenin equivalent voltage due to $V_{dd}$ from the first stage, the Thevenin equivalent voltage due to $V_{in}$, the PSRR, the DC PSRR value, the zero, the pole, and the PGB.

From Figure 9(b), the Thevenin equivalent voltage due to$V_{dd}$is given by $V_{out1}=b_2{V}_{dd}$. While:

$$b_2\approx {\displaystyle \frac{g_{m1}{r}_{o1}{r}_{o5}}{\frac{1}{2g_{m3}}+g_{m1}{r}_{o1}{r}_{o5}}}\approx {\displaystyle \frac{2g_{m1}{r}_{o1}{g}_{m3}{r}_{o5}}{1+2g_{m1}{r}_{o1}{g}_{m3}{r}_{o5}}}\approx 1,$$

(19)

Similarly, the Thevenin equivalent voltage due to $V_{in}$is $A{V}_{in}$ :

$$A=g_{m1}(r_{o2}||r_{o4}),$$

(20)

Using the node current equations, we obtain

$$V_1={\displaystyle \frac{(b+Rs{C}_1)V_{dd}+(A+Rs{C}_C)V_o}{1+Rs(C_1+C_2+C_C)}},$$

(21)

$$V_o{\displaystyle \frac{V_{dd}(g_{m6}+\frac{1}{r_{o6}})+V_o[(\frac{1}{r_{o6}}+\frac{1}{r_{o7}})+s(C_C+C_L)]}{g_{m6}-s{C}_C}},$$

(22)

Equating (21) and (22) yields:

$$\begin{array}{l}{V}_o\{(g_{m6}-s{C}_C)（\mathrm{A}+Rs{C}_C)+[({\displaystyle \frac{1}{r_{o6}}}+{\displaystyle \frac{1}{r_{o7}}})+s(C_C+C_L)][1+Rs(C_1+C_C+C_L)]\}\\ =Vdd\{(g_{m6}+{\displaystyle \frac{1}{r_{o6}}})[1+Rs(C_1+C_C+C_L)]+(b_2+Rs{C}_1)(-g_{m6}+s{C}_C)\}\end{array},$$

(23)

PSRR Calculation:

Under the assumptions that $Z_1\ll Z_2$ ,$C_2\ll C_C$, approximate expressions for the DC PSRR value and the zero can be derived as

$${\displaystyle \frac{1}{|PSRR(s)|}}={\displaystyle \frac{\frac{g_{m6}}{1+2g_{m1}{r}_{o1}{g}_{m3}{r}_{o5}}+\frac{1}{r_{o6}}}{A{g}_{m6}+(\frac{1}{r_{o7}}+\frac{1}{r_{o6}})}}\approx {\displaystyle \frac{\frac{1}{r_{o6}}}{A{g}_{m6}}}={\displaystyle \frac{1}{A{g}_{m6}{r}_{o6}}},$$

(24)

$$Z_1\approx -{\displaystyle \frac{1}{g_{m6}{r}_{o6}R(C_2+C_C)}},$$

(25)

$$Z_2\approx -{\displaystyle \frac{g_{m6}}{C_1}},$$

(26)

Assuming that $P_1\ll P_2$,$C_L\ll C_C$,$C_1\ll C_C$, $g_{m1}\ll g_{m6}$, he pole of the PSRR is approximately given by:

$$P_1\approx \frac{g_{m6}}{C_C}=\mathit{GB},$$

(27)

$$P_2\approx -{\displaystyle \frac{g_{m6}}{C_1+C_2+C_L}}=GB,$$

(28)

$${\displaystyle \frac{1}{PSRR(s)}}={\displaystyle \frac{1}{A{g}_{m6}{r}_{o6}}}\times {\displaystyle \frac{(1+g_{m6}{r}_{o6}Rs(C_2+C_C))(1+s\frac{C_1}{g_{m6}})}{(1+\frac{s}{GB})(1+s\frac{C_1+C_2+C_L}{g_{m6}})}},$$

(29)

Similarly, the calculation of PGB follows the same procedure as described previously.

From (30), it is apparent that the PGB of the N-input is relatively smaller. It is evident that by increasing the output resistance R of the first stage and the small-signal resistance R_O6 of M₆, the DC PSRR value improves. However, the ${\omega }_{-3dB}$ point shifts closer to the origin, thereby enhancing only the low-frequency portion of the response, while the PGB remains unchanged. Under stability constraints, reducing C_C shifts ${\omega }_{-3dB}$ away from the origin and improves the frequency characteristics. Comparing the PGB values for the P-input and N-input two-stage op-amps (under ideal bias conditions), the frequency response of the P-input op-amp is superior by an order of magnitude.

2.2.1. P-Input Folded Cascode Op-Amps

The folded cascode structure is an efficient design for the op-amp input stage, significantly increasing the input impedance and gain while improving the power supply rejection. Following the approach used for the P- and N-input two-stage op-amps, we analyze the common P-input folded cascode op-amp structure and derive the relevant equations.

Figure 10. P-input folded cascode op-amp.

Figure 10. P-input folded cascode op-amp.

Using the Thevenin theorem, we first derive the open-circuit output voltage of the first stage. This open-circuit voltage can be computed by applying the superposition principle. The analytical approach is similar to that for the P- and N-input two-stage op-amps. First, the effect of the drain input signal from M₅ on the output is calculated. The circuit is modeled using the small-signal equivalent, and further simplified via Norton’s theorem, as shown in Figure 11, yielding a Thevenin equivalent voltage of $V_{out1}=b_3{V}_{dd}$, and:

$$d_2=C_{o1}{C}_C+C_{out}(C_{o1}+C_C),$$

(31)

Figure 11. Equivalent circuit for the folded cascode op-amp.

Figure 11. Equivalent circuit for the folded cascode op-amp.

Next, we calculate the effects of the drain input signals from M₃ and M₄ on the output. The resulting Thevenin equivalent voltage is $V_{out1}=m_1{V}_{dd}$.

$$\begin{array}{l}{m}_1\approx {\displaystyle \frac{g_{m11}{r}_{o11}\times (0.5r_{o7})\left|\right|(g_{m1}{r}_{o1}{r}_{o5})}{0.5(\frac{1}{g_{m3}}+\frac{1}{g_{m9}})+g_{m11}{r}_{o11}\times (0.5r_{o7})\left|\right|(g_{m1}{r}_{o1}{r}_{o5})}}\approx {\displaystyle \frac{0.5g_{m11}{r}_{o11}{r}_{o7}}{0.5(\frac{1}{g_{m3}}+\frac{1}{g_{m9}})+0.5g_{m11}{r}_{o11}{r}_{o7}}}\\ ={\displaystyle \frac{g_{m3}{g}_{m11}{r}_{o11}{r}_{o7}}{g_{m3}{g}_{m11}{r}_{o11}{r}_{o7}}}\end{array},$$

(32)

where it is found that $m_1\approx 1$.

Subsequently, the effect of ${\displaystyle \frac{1}{PSRR(s)}}={\displaystyle \frac{V_o}{V_{dd}}}$ on the output is computed; as shown in Figure 12, the Thevenin equivalent voltage induced by $\begin{array}{c}{\displaystyle \frac{1}{|PSRR(s)|}}={\displaystyle \frac{\frac{1}{r_{o6}}+[1-(1+\frac{g_{m6}}{g_{m9}})\frac{g_{m6}{r}_{o6}}{g_{m3}{r}_{o6}}}{g_{m6}A+(\frac{1}{r_{o6}}+\frac{1}{r_{o13}})}}\\ \approx {\displaystyle \frac{1-(1+\frac{g_{m3}}{g_{m9}})\frac{g_{m6}{r}_{o6}}{g_{m9}-g_{m3}{r}_{o5}}}{g_{m6}{r}_{o6}A}}\end{array}$is -A$\begin{array}{c}{Z}_1=-{\displaystyle \frac{\frac{1}{r_{o6}}+[1-(1+\frac{g_{m3}}{g_{m9}})\frac{g_{m6}{r}_{o6}}{g_{m3}{r}_{o5}}}{R(g_{m6}+\frac{1}{r_{o6}})(C_1+C_2+C_C)+(b{C}_C-g_{m6}R{C}_1)}}\\ \approx -{\displaystyle \frac{1-(1+\frac{g_{m3}}{g_{m9}})\frac{g_{m6}{r}_{o6}}{g_{m3}{r}_{o5}}}{g_{m6}{r}_{o6}R(C_2+C_C)}}\end{array}$ Finally, by applying the superposition theorem, the circuit is reduced to its simplest form:

$R=g_{m9}{r}_{o9}{r}_{o9}||g_{m11}{r}_{o11}{r}_{o7}$ denotes the output resistance of the first stage. To calculate the PSRR, the values of $v_o$ and $v_{\mathit{dd}}$ must be determined. Based on the circuit diagram, we write the node current equation at $v_o$: which simplifies to:

$${\displaystyle \frac{V_o}{V_{dd}}}={\displaystyle \frac{(b_3+m_1)+Rs{C}_2}{(A+1)+Rs(C_1+C_2)}}\approx {\displaystyle \frac{1+Rs{C}_2}{A+Rs(C_1+C_2)}},$$

(34)

$$\because b_3+m_1\approx 1$$

$${\displaystyle \frac{1}{PSRR(s)}}={\displaystyle \frac{V_o}{V_{dd}}}\approx {\displaystyle \frac{1}{A}}\times {\displaystyle \frac{1+Rs{C}_2}{1+\frac{Rs(C_1+C_2)}{A}}}={\displaystyle \frac{1}{A}}\times {\displaystyle \frac{1+Rs{C}_2}{1+\frac{s(C_1+C_2)}{g_{m1}}}},$$

(35)

$${\displaystyle \frac{1}{|PSRR(s)|}}={\displaystyle \frac{1}{A}},$$

(36)

$$Z=-{\displaystyle \frac{1}{R{C}_2}},$$

(37)

$$P=-{\displaystyle \frac{g_{m1}}{C_1+C_2}},$$

(38)

In this example, $R=g_{m9}{r}_{o9}{r}_{o9}\left|\right|g_{m11}{r}_{o11}{r}_{o7}$. The inverse of the DC PSRR value is equal to the op-amp gain. The PGB is then derived as:

$$PGB=|Z\times PSRR|={\displaystyle \frac{A}{R{C}_2}}={\displaystyle \frac{g_{m1}}{C_2}},$$

(39)

Key design insights include:

(a)

Increasing g_m1 directly raises the DC PSRR value.

(b)

Reducing the parasitic capacitance C₂ improves the frequency response.

(c)

The dominant pole of the op-amp is associated with its output node. Consequently, augmenting C₁ shifts this pole closer to the origin, which is advantageous for enhancing both system stability and the frequency response of the PSRR. However, it is crucial to strike a balance with the required bandwidth; one cannot indiscriminately reduce the bandwidth without considering the overall system performance requirements.

2.2.1. N-Input Folded Cascode Op-Amps

Following the approach in Section 2.2.3, we analyze the N-input folded cascode op-amp. The simplified flowchart for a typical N-input two-stage op-amp is consolidated in Figure 13.

From the Thevenin equivalent circuit, we obtain:

$$V_1=V_{dd}{\displaystyle \frac{g_{m1}{r}_{o1}{r}_{o5}}{0.5r_{o5}+g_{m1}{r}_{o1}{r}_{o5}}},$$

(40)

$$V_{dd}-V_1=V_{dd}{\displaystyle \frac{0.5r_{o5}}{0.5r_{o5}+g_{m1}{r}_{o1}{r}_{o5}}},$$

(41)

$$V_{open}=V_1-2g_{m11}(V_{dd}-V_1)\times 0.5r_{o11}=V_{dd}{\displaystyle \frac{g_{m1}{r}_{o1}{r}_{o5}-g_{m11}{r}_{o11}{r}_{o7}}{0.5r_{o7}+g_{m1}{r}_{o1}{r}_{o5}}}\approx V_{dd}(1-{\displaystyle \frac{g_{m11}{r}_{o11}{r}_{o7}}{2g_{m1}{r}_{o1}{r}_{o5}}}),$$

(42)

where the equivalent resistance is $R_{out}\approx 0.5g_{m11}{r}_{o11}{r}_{o7}$

Using resistive voltage division, the Thevenin equivalent voltage is found to be $V_{out1}=b_4{V}_{dd}$。

$$b_4\approx {\displaystyle \frac{1+\frac{g_{m3}}{g_{m9}}}{g_{m11}{r}_{o11}{g}_{m3}{r}_{o7}}},$$

(43)

The Thevenin equivalent voltage induced by $V_{in}$ is $-A{V}_{in}$:

$$A=g_{m1}(g_{m9}{r}_{o9}{r}_{o7}||g_{m11}{r}_{o11}{r}_{o7}),$$

(44)

Where $R=g_{m9}{r}_{o9}{r}_{o9}\left|\right|g_{m11}{r}_{o11}{r}_{o7}$ denotes the output resistance of the first stage. By writing the node current equation at node $V_o$ , the relationship between $V_{dd}$ and $V_o$ is obtained:

$$V_{dd}(b+Rs{C}_2)=V_o[(A+1)+Rs(C_1+C_2)],$$

(45)

Subsequently, the PSRR is calculated as

$${\displaystyle \frac{1}{|PSRR(s)|}}={\displaystyle \frac{1+\frac{g_{m3}}{g_{m9}}}{g_{m11}{r}_{o11}{g}_{m3}{r}_{o7}A}},$$

(46)

$$Z=-{\displaystyle \frac{1+g_{m9}}{g_{m11}{r}_{o11}{g}_{m3}{r}_{o7}R{C}_2}},$$

(47)

$$P=-{\displaystyle \frac{g_{m1}}{C_1+C_2}},$$

(48)

$C_1$ is the compensation capacitor and $C_2$ represents the parasitic capacitance. Since the op-amp’s input resistance R is very high, the zero is located near the origin, while the pole is far from the origin:

$$PGB=|Z\times PSRR|=-{\displaystyle \frac{1+\frac{g_{m3}}{g_{m9}}}{g_{m11}{r}_{o11}{g}_{m3}{r}_{o7}R{C}_2}}\times {\displaystyle \frac{g_{m11}{r}_{o11}{g}_{m3}{r}_{o7}A}{1+\frac{g_{m3}}{g_{m9}}}}={\displaystyle \frac{g_{m1}}{C_2}},$$

(49)

3. Results and Discussions

In this section, we will apply the proposed method to design a fully differential op amp with high PSRR. The circuit was designed using Cadence Virtuoso IC617 with a 180 nm CMOS process. We will first list the calculation process of several important indicators, and find the aspect ratio of each transistor through the constraints of multiple indicators. Then compare the simulation results with the calculation results to verify the accuracy of the PSRR calculation method

At the same time, we use the PGB formula to more intuitively know how to improve the PSRR of this complex circuit. We performed a simulation and verified the correctness of the PGB theory by comparing the PSRR before and after the modification.

At the end of this section, the simulation results of the circuit are given, and the expected indicators and the size of each transistor are given in a table at the end of the chapter for reference.

Figure 14. Circuit architecture.

Figure 14. Circuit architecture.

(a)

Gain Expression

The transconductance of the input stage, G_m1, is given as:

$$G_{m1}=g_{m1},$$

(50)

The voltage gain is expressed as:

$$A_{v1}=-g_{m1}\{[g_{m7}{r}_{o7}(r_{o1}|\left|r_{o9a}\right||r_{o9b})]||(g_{m5}{r}_{o5}{r}_{o3})\},$$

(51)

$$A_{v2}=-G_{m2}{R}_{o2}=-g_{m13}(r_{o11}||r_{o13}),$$

(52)

$$A_{dm}=A_{v1}·A_{v2},$$

(53)

• (b) Transfer Function Optimization

As illustrated in Figure 15, the feedforward stage introduces a zero-pole pair in the transfer function, compensating for the dominant pole. This minimizes phase lag and extends the high-frequency bandwidth. The transfer function is given by

$$A_v(s)={\displaystyle \frac{s[g_{mf1}(C_{o1}+C_C)-g_{m1}{C}_C]+g_{mf1}{g}_{o1}+g_{m1}{g}_{mL}}{s^2{d}_2+s{d}_1+d_0}},$$

(54)

Where:

$$d_2=C_{o1}{C}_C+C_{out}(C_{o1}+C_C)$$

$$d_1=g_{o1}{C}_{out}+g_{out}(C_{o1}+C_C)+(g_{o1}+g_{mL})C_C$$

$$d_0=g_{o1}{g}_{out}$$

$$g_{o1}={\displaystyle \frac{1}{R_{o1}}}$$

• (c) PSRR

We calculate the PSRR using the method presented in Chapter II. Referring to Figure 10. in Chapter II, the first stage of op amps can be equivalent to $V_{out}=(b_3+m_1)V_{dd}+A{V}_{in}$, Where:

$$b_3\approx (1+{\displaystyle \frac{g_{m3}}{g_{m6}}}){\displaystyle \frac{1}{g_{m3}{r}_{o0}}},$$

(55)

$$m_1={\displaystyle \frac{g_{m3}{g}_{m11}{r}_{o7}(r_{o9a}||r_{o9b})}{g_{m3}{g}_{m11}{r}_{o7}(r_{o9a}||r_{o9b})}}=1,$$

(56)

Referring to the calculation in Figure 9., replace the original b with here and replace with the transfer function of PSRR that can be obtained directly

$${\displaystyle \frac{1}{PSRR(s)}}={\displaystyle \frac{V_o}{V_{dd}}},$$

(57)

Assuming $Z_1\ll Z_2$,$C_1\ll C_C$,$C_1=C_{gb14}+C_{db6}+C_{db8}$,$r_{o9}\text{'}=r_{o9a}\left|\right|r_{o9b}$,$C_{gd9}\text{'}=C_{gd9a}\left|\right|C_{gd9b}$

$${\displaystyle \frac{1}{|PSRR(s)|}}={\displaystyle \frac{\frac{1}{r_{o6}}+[1-(1+\frac{g_{m14}}{g_{m5}})\frac{g_{m14}{r}_{o14}}{g_{m3}{r}_{o14}}}{g_{m14}A+(\frac{1}{r_{o14}}+\frac{1}{r_{o12}})}}\approx {\displaystyle \frac{1-(1+\frac{g_{m3}}{g_{m5}})\frac{g_{m14}{r}_{o14}}{g_{m5}-g_{m3}{r}_{oo}}}{g_{m14}{r}_{o14}A}}$$

(58)

$$Z_1=-{\displaystyle \frac{\frac{1}{r_{o14}}+[1-(1+\frac{g_{m3}}{g_{m5}})\frac{g_{m14}{r}_{o14}}{g_{m3}{r}_{oo}}}{R(g_{m14}+\frac{1}{r_{o14}})(C_{gs14}+C_1+C_C)+(b_3{C}_C-g_{m14}R{C}_{gs14})}}\approx -{\displaystyle \frac{1-(1+\frac{g_{m3}}{g_m})\frac{g_{m14}{r}_{o14}}{g_{m3}{r}_{oo}}}{g_{m14}{r}_{o14}R(C_1+C_C)}},$$

(59)

$$Z_2=-{\displaystyle \frac{R(g_{m14}+\frac{1}{r_{o14}})(C_{gs14}+C_1+C_C)+(b_3{C}_C-g_{m14}R{C}_{gs14})}{R{C}_{gs14}{C}_C}}\approx -{\displaystyle \frac{g_{m14}R(C_1+C_C)}{R{C}_{gs14}{C}_C}}\approx -{\displaystyle \frac{g_{m14}}{C_{gs14}}}$$

(60)

If $P_1\ll P_2$,$C_1\ll C_C$,$C_L\ll C_C$:

$$P_1\approx {\displaystyle \frac{-[g_{m14}A+(\frac{1}{r_{o14}}+\frac{1}{r_{o9}\text{'}})]}{(g_{m14}-g_{m1})R{C}_C+R(\frac{1}{r_{o14}}+\frac{1}{r_{o9}\text{'}})(C_{gd14}+C_C)+(C_{gd9}\text{'}+C_L+C_C)}}\approx -{\displaystyle \frac{g_{m14}A}{(g_{m14}-g_{m1})R{C}_C}}\approx -{\displaystyle \frac{g_{m14}{g}_{m1}}{(g_{m14}-g_{m1})R{C}_C}}\approx -{\displaystyle \frac{g_{m1}}{C_C}}=\mathrm{GB}$$

(61)

$$P_2=-{\displaystyle \frac{g_{m6}}{C_{gs14}+C{}_L+(C_{gd9a}||C_{gd9b})}},$$

(62)

$${\displaystyle \frac{1}{PSRR(s)}}={\displaystyle \frac{1-(1+\frac{g_{m3}}{g_{m2}})\frac{g_{m14}{r}_{o14}}{g_{m3}{r}_{o0}}}{g_{m14}{r}_{o14}A}}\times {\displaystyle \frac{(1+\frac{g_{m14}{r}_{o14}(C_1+C_C)s}{g_{m6}{r}_{o6}})(1+\frac{C_{gs14}}{g_{m14}}s)}{(1+\frac{s}{GB})(1+\frac{C_{gs14}+C_1+C_C}{g_{m14}}s)}},$$

(63)

$$PGB=|Z_1\times PSRR|=|{\displaystyle \frac{1-(1+\frac{g_{m3}}{g_{m5}})\frac{g_{m14}{r}_{o14}}{g_{m5}}}{g_{m14}{r}_{o14}R(C_1+C_C)}}\times {\displaystyle \frac{g_{m14}{r}_{o14}A}{1-(1+\frac{g_{m3}}{g_{m5}})\frac{g_{m14}{r}_{o14}}{g_{m3}{r}_{o0}}}}|={\displaystyle \frac{g_{m1}}{C_1+C_C}},$$

(64)

Constrained by the above formula, we can easily find the size of each transistor. Table 1 shows the design specifications of this circuit.

And after simulation, we hope to further optimize the performance of PSRR. Compared with the traditional analysis of PSR in the industrial method, we know more intuitively that we can enhance the performance of PSRR by increasing gm or reducing cc according to (64). The simulation results before and after the modification are shown below:

Figure 17. PSR simulation experiment.

Figure 17. PSR simulation experiment.

Figure 18. PSRR simulation experiment.

Figure 18. PSRR simulation experiment.

As shown in the above, the modified circuit has improved DC gain performance due to the increase in the width of the input transistor. In addition, the performance of PSR and PSRR is even better, which verifies the ability of PGB to help analog circuit designers improve PSRR more intuitively in complex circuits.

We also performed some other simulations on the circuit. Figure 19 shows the basic indicators of the circuit at different process corners, and Figure 19-d shows the PSRR of the circuit at each process corner after PGB operation adjustment

The PSRR of this circuit is more than 100dB at 100kHz for all process conners. It is also very good at high frequencies. We also did a Monte Carlo simulation, and the results are shown in the Figure 20.

$${\displaystyle \frac{V_o}{V_{dd}}}={\displaystyle \frac{(b_3+m_1)+Rs{C}_2}{(A+1)+Rs(C_1+C_2)}}\approx {\displaystyle \frac{1+Rs{C}_2}{A+Rs(C_1+C_2)}}$$

$$\mathit{FOM}=\frac{\mathit{GBW}\times C_L}{\mathit{TotalPower}}$$

Table 2 shows the simulation results of this circuit and the comparison with other high PSRR op amps. Table 3 shows the comparison between the expected performance and simulation results of the circuit designed using our proposed PSRR calculation method. The design requirements are achieved in all indicators and a good FOM value is achieved. The PSRR calculation method proposed in this article provides a new idea for future circuit design, and the PGB optimization method can also simplify the complex process of PSR calculation.

4. Conclusions

Experimental validation in Section III demonstrates that by leveraging Thevenin’s equivalence principle, the proposed method transforms multi-stage op-amps into simplified black-box models, significantly reducing computational complexity while enhancing intuitive analysis. The introduced PGB metric, which correlates the DC PSRR value with the first dominant pole frequency, eliminates the reliance on exhaustive S-parameter modeling. This enables a computationally efficient evaluation of PSRR performance within the target frequency band. While the PGB framework assumes validity primarily below the GBW—a constraint inherent to its first-order approximation—it remains highly practical for industrial design scenarios where critical PSRR specifications typically reside in low-to-mid frequency ranges. the PGB metric provides actionable insights for optimizing PSRR through parameter adjustments and facilitates rapid comparative analysis of competing circuit topologies.

The proposed framework not only simplifies PSRR analysis for asymmetric and multi-stage circuits but also provides actionable insights for optimizing key parameters (e.g., transconductance, compensation capacitance) to meet stringent industrial requirements. Future work will extend this approach to mixed-signal systems and explore its integration with machine learning-driven design automation tools.