Tsmots, I.; Teslyuk, V.; Łukaszewicz, A.; Lukashchuk, Y.; Kazymyra, I.; Holovatyy, A.; Opotyak, Y. An Approach to the Implementation of a Neural Network for Cryptographic Protection of Data Transmission at UAV. Drones2023, 7, 507.
Tsmots, I.; Teslyuk, V.; Łukaszewicz, A.; Lukashchuk, Y.; Kazymyra, I.; Holovatyy, A.; Opotyak, Y. An Approach to the Implementation of a Neural Network for Cryptographic Protection of Data Transmission at UAV. Drones 2023, 7, 507.
Tsmots, I.; Teslyuk, V.; Łukaszewicz, A.; Lukashchuk, Y.; Kazymyra, I.; Holovatyy, A.; Opotyak, Y. An Approach to the Implementation of a Neural Network for Cryptographic Protection of Data Transmission at UAV. Drones2023, 7, 507.
Tsmots, I.; Teslyuk, V.; Łukaszewicz, A.; Lukashchuk, Y.; Kazymyra, I.; Holovatyy, A.; Opotyak, Y. An Approach to the Implementation of a Neural Network for Cryptographic Protection of Data Transmission at UAV. Drones 2023, 7, 507.
Abstract
An approach to the implementation of neural network for real-time cryptographic data protection with symmetric keys oriented on embedded systems is presented. This approach is valuable especially for onboard communication systems in unmanned aerial vehicles (UAV) because of suitability to hardware implementation. In this study we evaluate the possibility to build such a system in hardware implementation at FPGA. The proposed integrated neural network approach for real-time cryptographic data protection was based on theoretical foundations of neural network cryptographic data protection, new algorithms and structures of neural network data encryption and decryption, modern hardware components with programmable structure. The development and implementation of the on-board neural network system for cryptographic data protection in real-time are based on the following principles: variable composition of equipment; modularity; conveyorization and spatial parallelism; hardware and software modification and making them suitable for data encryption and decryption. The tabular-algorithmic method for calculation of the scalar product has been improved that makes it possible to perform fast calculation of the scalar product of fixed-point and floating-point input data by bringing them to the largest common order of weights and forming tables of macro-partial products. Components of neural network cryptographic data encryption and decryption have been developed on the processor core supplemented by specialized scalar product calculation modules. The specialized hardware for neural network cryptographic data encryption was developed using VHDL for equipment programming in the Quartus II development environment ver. 13.1 and the appropriate libraries, and implemented on the basis of the FPGA EP3C16F484C6 Cyclone III family.
Copyright:
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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