An attractive option for realizing applications in radiation environments is to employ All-Programmable System-on-Chips (APSoCs) thanks to their high-performance computing and power efficiency merits. Despite APSoC's advantages, like any other electronic device, they are prone to radiation effects. Processors found in APSoCs must, therefore, be adequately hardened against ionizing-radiation to become a viable alternative for harsh environments. This paper proposes a novel triple-core lockstep (TCLS) approach to secure the Xilinx Zynq-7000 APSoC dual-core ARM Cortex-A9 processor against radiation-induced soft errors by coupling it with a MicroBlaze TMR subsystem in Zynq's programmable logic (PL) layer. The proposed strategy uses software-level checkpointing principles along with roll-back and roll-forward mechanisms (i.e. software redundancy), and hardware-level processor replication as well as checker circuits (i.e. hardware redundancy). Results of fault injection experiments show that the proposed solution achieved high soft error security by mitigating about 99% of bit-flips injected into both ARM cores' register data.

Optical neural networks (ONNs), or optical neuromorphic hardware accelerators, have the potential to dramatically enhance the computing power and energy efficiency of mainstream electronic processors, due to their ultra-large bandwidths of up to 10’s of terahertz together with their analog architecture that avoids the need for reading and writing data back-and-forth. Different multiplexing techniques have been demonstrated to demonstrate ONNs, amongst which wavelength-division multiplexing (WDM) techniques make sufficient use of the unique advantages of optics in terms of broad bandwidths. Here, we review recent advances in WDM-based ONNs, focusing on methods that use integrated microcombs to implement ONNs. We present results for human image processing using an optical convolution accelerator operating at 11 Tera operations per second. The open challenges and limitations of ONNs that need to be addressed for future applications are also discussed.

The advantage of FPGAs lies in the ability to implement a fully hardware solution for interfacing with various input/output (I/O) devices. Each block can work in parallel with all the others, simplifying the satisfaction of timing constraints. However, this hardware utilization consumes FPGA resources that could otherwise be allocated to the primary project. An alternative involves employing a small "soft-core" processor implementing I/O in software. With the goal to design and evaluate a new tiny soft-core processor optimized for FPGA resources in I/O , a novel processor named Baby8 is developed. It is an 8-bit CISC soft-core processor optimized for reduced FPGA resources including program size for 8-bit applications. The number of instructions is not large but any instruction can access arbitrary memory locations. The performance and resource utilization of the newly designed processor are evaluated and compared with a variety of other soft-core processors. The results demonstrate its competitive performance, achieving an average maximum clock frequency of approximately 57 MHz and a power consumption of around 2mW. Furthermore, it conserves nearly half of the FPGA resources in implementation.

The chicken poultry business is becoming a crucial sector for our nation's sustainable food supply. To increase the health of chickens in coops and maybe increase the output of chicken meat and eggs, several innovations and inventions have been developed. Therefore, the creation of an automated chicken feeding device might be highly beneficial for the expansion of the poultry sector. This equipment may take the role of a worker in the chicken feeding process, solving the industry's labor shortage and introducing a semi-automatic procedure. The main processor of the automated chicken feeding system is a Raspberry Pi 3 Model B+. The machine consists of five main components: a Raspberry Pi with an amplifier that makes noise to draw the attention of free-range chickens, a Raspberry Pi with a pi camera that counts and detects the chickens, a Raspberry Pi with a servomotor that moves the food from storage to a container, a Raspberry Pi with a load cell that controls the number of feeds to avoid waste on foods, and a Raspberry Pi with a temperature sensor that monitors the food's freshness. This enhances the coop's atmosphere while lowering labor costs, conserving food, and ensuring that the chickens are fed on time. It also regulates the temperature sensor to ensure that the chicken food is fresh and prevents food from becoming polluted by insects and chicken excrement.

Millions of people worldwide experience visual problems nowadays. According to the recent WHO survey, approximately…… million people are blind. They become reliant on others because of this issue. According to recent studies, 108 various techniques are utilized to help the moment of people who are visually impaired. In this research we will employ infrasonic sound to improve the ability of blind persons to identify obstacles that comes in its way at the distance ranging from 2 to 3.5 maters. The concept was created by drawing inspiration from a mammal termed certain animals inherent navigational system. The infrasonic detection for the visually impaired people is a complicated procedures ,now we will simply discuss the obstacle finding mechanism in this article. The project uses an Arduino UNO microcontroller, infrasonic sensors, a buzzer powered by 5 volts , a vibrator, burning Arduino cable and a few connecting wires. On a cap that the blind people will wear all of this arrangement will be placed. High frequency sound is emitted by the infrasonic emitter picked up by the infrasonic receiver after reflecting off of the obstruction and then transmitted to the processor for additional required activity in the form of sound and vibration.

This work introduces a novel facial image capture system that utilizes computer vision technology and artificial intelligence for real-time detecting, tracking, and capturing of human faces. The objective of this study is to address the challenges posed by poor-quality facial images in biometric authentication, especially in passport photo acquisition and recognition. By combining face-aware capture technology with AES encryption for secure image storage, we present a completely open-source hardware solution that consists of a Jetson processor, a 16MP autofocus RGB camera, a custom enclosure, and a touch sensor LCD for user interaction. Pilot data collection demonstrates the system's ability to capture high-quality images, achieving a 98.98% accuracy in storing images of acceptable quality. The integration of AES encryption ensures data security, making the proposed system suitable for real-time applications in other domains beyond identity verification in passport applications, such as security systems, video conferencing, etc

To increase the efficiency of fuel processor and HT-PEMFC (High Temperature-Proton Exchange Membrane Fuel Cell) combined system, it is essential to improve the efficiency of a fuel processor. In this research, the fuel processor was simulated by Aspen Hysys® simulator, and effect of the various operating conditions on the total efficiency was investigated. Thermal efficiency of the fuel processor increased as the temperature and S/C (Steam to carbon) ratio increased, and the efficiency was higher at the S/C ratio of 3 than at the S/C of 4 at the reformer temperature of 700 ℃ and higher. Under the selected operating conditions of the fuel processor, recycling of unreacted hydrogen from the anode off gas (AOG) of the HT-PEMFC improve the overall efficiency of the combined fuel processer and HT-PEMFC by a factor of 1.28. Operating conditions where the AOG supplied excessive heat than required for fuel processor operation were excluded. The high-efficiency operating conditions of the fuel cell system were proposed with the target of 5 kW of output as the capacity of the household HT-PEMFC.

Many dedicated designs for real-time operations provide functionality on fixed-sized operators, but where speed, scalability, and flexibility are required, extensive research is demanded. Dedicated designs can provide real-time processing for many applications. This paper presents an FPGA-based design of a general image processor. The proposed design is based on a fixed-point representation of binary numbers. The proposed design provides a mechanism to manage matrices on-chip along with matrix arithmetic. The matrices are represented with simple identifiers and microinstruction that assist in the computation of many operations which are useful for solving complex problems. The design was successfully implemented and tested using VHDL language. The proposed design is an efficient architecture as a standalone processor with all embedding computational resources necessary for an embedded image processing application.