Working Paper Article Version 2 This version is not peer-reviewed

Novel Lockstep-based Approach with Roll-back and Roll-forward Recovery to Mitigate Radiation-Induced Soft Errors

Version 1 : Received: 4 June 2020 / Approved: 5 June 2020 / Online: 5 June 2020 (14:34:52 CEST)
Version 2 : Received: 7 August 2020 / Approved: 8 August 2020 / Online: 8 August 2020 (04:57:57 CEST)

How to cite: Kasap, S.; Wächter, E.W.; Zhai, X.; Ehsan, S.; McDonald-Maier, K. Novel Lockstep-based Approach with Roll-back and Roll-forward Recovery to Mitigate Radiation-Induced Soft Errors. Preprints 2020, 2020060055 Kasap, S.; Wächter, E.W.; Zhai, X.; Ehsan, S.; McDonald-Maier, K. Novel Lockstep-based Approach with Roll-back and Roll-forward Recovery to Mitigate Radiation-Induced Soft Errors. Preprints 2020, 2020060055

Abstract

An attractive option for realizing applications in radiation environments is to employ All-Programmable System-on-Chips (APSoCs) thanks to their high-performance computing and power efficiency merits. Despite APSoC's advantages, like any other electronic device, they are prone to radiation effects. Processors found in APSoCs must, therefore, be adequately hardened against ionizing-radiation to become a viable alternative for harsh environments. This paper proposes a novel triple-core lockstep (TCLS) approach to secure the Xilinx Zynq-7000 APSoC dual-core ARM Cortex-A9 processor against radiation-induced soft errors by coupling it with a MicroBlaze TMR subsystem in Zynq's programmable logic (PL) layer. The proposed strategy uses software-level checkpointing principles along with roll-back and roll-forward mechanisms (i.e. software redundancy), and hardware-level processor replication as well as checker circuits (i.e. hardware redundancy). Results of fault injection experiments show that the proposed solution achieved high soft error security by mitigating about 99% of bit-flips injected into both ARM cores' register data.

Subject Areas

Lockstep; Reliability; Fault Tolerance; Soft Error Mitigation; Zynq APSoC; ARM Cortex-A Processor; MicroBlaze Processor

Comments (1)

Comment 1
Received: 8 August 2020
Commenter: Server Kasap
Commenter's Conflict of Interests: Author
Comment: I have changed the title of the page plus have done minor changes to the paper.
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