Concept Paper
Version 1
Preserved in Portico This version is not peer-reviewed
Digital Design of Programmable Image Processor for FPGA
Version 1
: Received: 14 April 2022 / Approved: 14 April 2022 / Online: 14 April 2022 (05:09:47 CEST)
How to cite: Khan, A. Digital Design of Programmable Image Processor for FPGA. Preprints 2022, 2022040129. https://doi.org/10.20944/preprints202204.0129.v1. Khan, A. Digital Design of Programmable Image Processor for FPGA. Preprints 2022, 2022040129. https://doi.org/10.20944/preprints202204.0129.v1.
Abstract
Many dedicated designs for real-time operations provide functionality on fixed-sized operators, but where speed, scalability, and flexibility are required, extensive research is demanded. Dedicated designs can provide real-time processing for many applications. This paper presents an FPGA-based design of a general image processor. The proposed design is based on a fixed-point representation of binary numbers. The proposed design provides a mechanism to manage matrices on-chip along with matrix arithmetic. The matrices are represented with simple identifiers and microinstruction that assist in the computation of many operations which are useful for solving complex problems. The design was successfully implemented and tested using VHDL language. The proposed design is an efficient architecture as a standalone processor with all embedding computational resources necessary for an embedded image processing application.
Supplementary and Associated Material
https://github.com/abdkhanstd/image\_processor: Codes and resources
Keywords
Digital Design; Digital Architecture; Image Processing; Machine learning; FPGA; Dedicated Design; Image Processor
Subject
MATHEMATICS & COMPUTER SCIENCE, Other
Copyright: This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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