Investigation of Short Channel Effects in Al0.30Ga0.60As Channel Based Junctionless Cylindrical Gate-All-Around FET for Low Power Applications

1. Introduction

Device miniaturization has been an essential technique for past years to meet the electronics industry's low-power, high-speed, and high-density chip needs [1, 2]. Due to aggressive scaling, transistors have been scaled down to nanometer dimensions close to physical limits [3, 4]. Industries utilize Moore's law to establish goals for R&D and direct long-term planning. Nonetheless, in the current context, Moore's law is approaching its limits, and conventional transistors (CTs) are becoming nanoscale in size, making the challenge of minimizing short-channel effects (SCEs) more important. To control the massive leakage currents and SCEs and pave the way further for transistor scaling, researchers have been looking into new technologies for non-conventional transistors (NCTs), such as SOI (Silicon on Insulator) MOS architecture, FinFET, Double Gate MOSFET (DG-MOSFET), and various Multigate MOSFET configurations [5].

CTs are replaced with novel transistors to meet the constant demand for high-frequency and low-power devices. Moore's law illustrates the exponential curve's decreasing size, where the number of transistors doubles every two years. This law was modified after a few years, increasing the number of transistors roughly every 18 months. The semiconductor companies have adopted his prognosis, which has been proven accurate. The International Technology Roadmap for Semiconductors (ITRS), a standard for the semiconductor industries, is updated using this regulation. It illustrated how the ITRS roadmap has changed over the years and demonstrated how this curve is saturating and leveling off at very high frequencies and in the current environment [6].

SCEs that impede the performance improvement of CMOS technology, such as SS, DIBL, mobility issues, parasitic capacitance, reliability, and breakdown phenomena, are becoming increasingly important to overcome in VLSI technology due to the shrinking CTs. There is a severe need to search for other architectures of various NCTs. Current research shows that in today's landscape, there are several performance benefits such as reduced drain-induced barrier lowering, leakage current reduction, improved I_on/I_off, better sub-threshold slope, low cost, and low power consumption of NCTs.

Various channel materials are used to enhance the performance of MOS devices, including strained silicon and germanium [7]. Lateral field diffusion is reduced, and the conducting channel is completely under gate control when MOS devices reach a specific scale in the submicron range. The lateral field is decreasing due to an increase in substrate doping. As the doping in the substrate grows, a strong bond between the substrate and the channel is formed, and the size of the depletion layer beneath the channel shrinks. A small amount of oxide is decreased in size to enhance the gate-channel interaction. Because of the gate oxide's shrinkage, threshold voltage control is required. The threshold voltage fluctuates more with a strongly doped substrate [7]. This process creates devices by placing tiny silicon pieces on a substrate, often an insulator like SiO₂. By using an insulating substrate to separate the Si layer from the wafer body, SOI lessens the impact of parasitic capacitances, which are caused by junction capacitances. Because of the presence of an insulator in SOI, the depletion region cannot be extended into the substrate. Hence, the capacitance at the junction is reduced, reducing RC delays and providing the high-speed performance of SOI devices at lower V_DD [8].

Two primary ways to obtain SOI devices are partially depleted SOI MOSFETs (PDSOI) and fully depleted SOI MOSFETs (FDSOI) [9]. PDSOI features a doped channel and a broad insulating buried oxide. Top Si typically has a thickness of 50–90 nm. For a partially depleted MOSFET, the silicon film thickness is more than the bulk depletion width; for a fully depleted MOSFET, it is less than the gate depletion width. Fully depleted MOSFETs are essentially free from KINK effects, although partially depleted MOSFETs are frequently affected by them; in PDSOI MOSFETs, a phenomenon known as the "kink effect" results in an abrupt rise in drain current. Injecting holes into the MOSFET's floating substrate causes this effect, which lowers the threshold voltage and raises the body potential. The cycle is repeated when more holes are created due to the increased drain current. In logic circuits, the kink effect helps with speed and current drive but hinders analog circuits' linearity. Controlling the carrier lifespan in the floating body region can lessen the kink effect. Adding back oxide to the device at specific locations beneath the source and drain is one way to accomplish this [10]. In FDSOI, a planar process method, the silicon substrate is positioned above a thin layer of insulator called the buried oxide. The transistor channel is formed by the minimum bulk thickness of 10 or 25 nm. It is, therefore, referred to as an ultra-thin body, and the buried oxide is UTBB FDSOI or fully depleted SOI. Low V_DD, which leads to low power consumption, less changeable V_T, low leakage, high logic density, minimal short channel effects, low DIBL, excellent SS, diode leakage, and minimum junction capacitance, is one of the many benefits of FDSOI. [11].

DG-MOSFETs are one of the most promising device topologies for future advancements in immunity against SCEs because of their capacity to regulate electrostatic integrity, or SCEs, in ultra-scaled MOS structures [12,13]. FinFET's optimal gate length to fin width ratio has made it a better choice with enhanced subthreshold slope and DIBL [14,15]. According to several research publications, FinFETs exhibit superior gate controllability, a lower SS, a larger Ion/Ioff ratio, and an improved DIBL compared to its regular planar equivalent. FinFET's non-planar characteristic promotes investigation of the multigate structure [16,17].

Due to device miniaturization technique or scaling, submicron and deep submicron technology have evolved, and simultaneously, SCEs are increasingly becoming more prominent in CTs. Source/drain, substrate, and gate engineering have provided solutions for addressing the leakage currents and reducing SCEs and narrow channel effects (NCEs). Geometrical edge effects are used to explain this narrow channel phenomenon. The transition from the field oxide depletion zone to the gate oxide depletion region becomes comparable to the gate width as the channel width decreases, making it impossible to ignore while determining the threshold voltage equation. The advent of the new device, JLFET, as a potential substitute for CTs, has come about due to the aggressive scaling of CTs during the era of nano-engineering or nanowires. In this work, cylindrical gate-all-around JLFETs have been thoroughly examined, and their performance has been evaluated compared to CTs. The outcomes of the study of JLFET hold significant relevance to the field of semiconductors and superconductors, especially in the context of energy-efficient electronic devices and integrated circuits. Due to device miniaturization, implanting junctions with doping concentrations ranging from 10¹⁹ to 10²⁰ cm^-3 within the nanoscale gate length is challenging [18]. Researchers have proposed the innovative idea of JLFET replacing CT. Since conventional MOSFETs cannot regulate SCEs, non-conventional JLFET architecture has emerged, and the findings indicate that JLFETs are more resistant to SCEs than CT [19].

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2. Mathematical Modelling of JLFET

JLFET is a kind of device fully depleted in the subthreshold region and moderately accumulated in the ON state. For both long- and short-channel cases, theoretical investigations have been performed on modeling cylindrical gate-all-around JLFETs. Notably, long-channel models lack the accuracy for short-channel cases. The advent of profound submicron technology has led to the increased requirement of integration density. The proposed study employs an analytical model based on the two-dimensional Poisson equation's estimated solution and subthreshold properties. [20]. The mathematical solutions for drain current under various bias conditions are shown in Table 1 and Table 2.

Table 1. Drain Current Equations for JLFET with Different Bias Conditions [20]

Table 1. Drain Current Equations for JLFET with Different Bias Conditions [20]

Table 2. The description of the symbol used in Table 1 [20]

Table 2. The description of the symbol used in Table 1 [20]

3. Theoretical and Simulation Framework

A junctionless transistor is a novel device that eliminates junctions and gradients in doping concentration. JLFET assists in resolving the difficulty of producing high-quality junctions in the semiconductor industry. A gate electrode modulates the resistivity of a strongly doped semiconductor bar in JLFETs, which can be considered a gated resistor. Metal-oxide-semiconductor field effect transistors (MOSFETs), the mainstay of the contemporary semiconductor industry, feature metallurgical junctions at the source-channel and channel-drain interfaces. In contrast, JLFETs are evenly doped and lack these junctions. In addition to a low thermal budget production procedure that is cheaper and easier, this results in several intriguing electrical features. Notably, the researchers have put forth several analytical and numerical approaches to solve the current transport mechanism in JLFET. The approach provides an analytical connection between surface potential models and gate voltage, focusing on Boltzmann statistics and the closed-form solution of Poisson's equation. The behavior of the device, including motion quantization, sub-band splitting, fermi statistics, quasi-ballistic transport, surface and channel orientation, and band structure, has been analyzed using numerical models.

Quasi-ballistic transport in nanowire field-effect transistors has been studied by Gnani et al. They used the one-dimensional Boltzmann transport equation to address the analytical solution for any possible profile while considering elastic scattering. They concluded that the kT layer has no bearing on one-dimensional quasi-ballistic carrier transport, and those inelastic collisions have little effect on nanowires [21]. The idea of the kT layer has caused criticism in the device modeling community because of the empirical character of the reasons that introduced it, even though Monte Carlo simulations provided quantitative validity. The theoretical foundation of the kT layer notion has been examined to improve comprehension [22]. It has been demonstrated that the Boltzmann Transport equation can be simplified to a formalism known as the "Quasi Ballistic drift-diffusion" formalism by taking into account one dimension in space, assuming non-degenerated statistics, one single isotropic band, and treating the collision integral by a simple "relaxation length" approximation. The distribution function could be artificially divided into two functions, one for positive velocity and one for negative velocity, both of which have a Maxwellian (thermal) shape and represent the concentration of carriers flowing from source to drain (or, more accurately, from drain to source), according to the BTE solution within these approximations. This method, which approximates semi-classical transport inside the relaxation length approximation framework, incorporates the effects of both arbitrary fields and isotropic scattering, making it a more comprehensive formalism than the kT layer model. Although it has long been known, its relationship to the kT layer notion has only lately been made clear. E. Gnani et al. explored band effects on the transport characteristics of ultra-scaled silicon nanowires, and the proposed model was validated by a tight binding approach and fitted transport effective masses [23]. Lenzi et al. have also used deterministic and Monte Carlo methodologies to solve the transport properties of nanowires. They have solved the coupled Schrodinger-Poisson equation to extract the potential profiles for one-dimensional and multi-dimensional sub-bands along the channel [24].

Using the non-equilibrium Green's function formalism, Poli et al. [25] offered insights into the solutions to the 3D Poisson-Boltzmann equation for comprehensive quantum treatment of Coulomb scattering in silicon nanowire FETs. JLFET is a multigate FET with no doping concentration gradients. Due to less and more manageable fabrication steps involved in JLFET, it is the best replacement for traditional CTs [26,27,28]. Tyndall's lab has created junction-less nanowire transistors with gate lengths as small as 50 nm [29]. The nanowires and the gates were patterned using electron beam lithography, and the gate oxide thickness was 5 nm. Because JLFETs have no junctions, their fabrication procedure is much more straightforward than conventional CTS and NCTs. Diffusion does not occur in JLFETs because there are no junction gradients between the source and drain. It dramatically reduces costs and eliminates the need for pricey annealing processes. The doping concentration in JLFETs typically varies from 10¹⁹ to 10²⁰ cm^-3 and is consistent and uniform throughout the device. Rather than relying on surface conductivity, the JLFET uses bulk conduction. The significant concern regarding the fabrication of JLFET is to make the semiconductor layer as thin and narrow to support the complete depletion of carriers in OFF condition, and the doping concentration should be as high to provide an excellent current drive in ON condition [30].

In the present scenario, researchers have provided evidence that III-V materials are more immune to SCEs than other CTs. These materials have become an essential substitute for silicon, and they play a massive role in the replacement of silicon and support the fabrication industry in the future. They have excellent current drive capability and high mobility without increasing gate capacitances. The influence of III-V material during manufacturing allows for precise bandgap and control over doping, compositions, and device dimensions. Using quantum mathematical simulations and suppression of source-drain tunneling, some researchers demonstrated the electrical performance of III-V materials, such as GaAs, and obtained currents of up to 100 nA/µm using a 0.65V power supply. According to certain studies, indium arsenide (InAs) is the ideal alternative to silicon channels because it has a low DIBL and an excellent subthreshold slope. Over the past fifty years, advancements in logic performance and an increase in the density of silicon complementary metal-oxide-semiconductor (CMOS) transistors have propelled the exponential growth in electronics power. However, silicon transistor scaling is currently at its limit and might end the revolution in microelectronics. Due to this, the focus is shifting to a family of materials called group III–V compound semiconductors. The construction of the first logic transistors at the nanometer scale may be greatly aided by these materials' exceptional electron transport capabilities. [31,32,33].

Nobrega et al. have compared silicon and III-V nanowire gate-all-around field effect transistors for different gate oxides. They simulated GaAs-based gate-all-around JLFET and reported SS with 58.2 mV/dec at 293.15 K, near the ideal 60 mV/dec [34]. Many research articles consider III-V material as a channel composition, such as germanium, gallium arsenide, indium arsenide, and indium phosphide [35]. Arefin et al. have discussed the impact of III-V material on the threshold voltage sensitivity of the device. They have provided results based on minimum and maximum threshold voltage variations for indium arsenide and silicon [36].

4. Device Structure of JLFET with III-V Materials

The three-dimensional JLFET with cylindrical gate-all-around design and III-V materials has undergone a thorough subthreshold study [37]. As shown in Figure 1, this proposed architecture has been comparatively studied with varying gate lengths of 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, and 60 nm with a constant radius of 14 nm. As shown in figure 1, this proposed device structure has been developed with the Al_0.30Ga_0.60As, Aluminium Gallium Arsenide (in composite form) as channel material having gate length varying from 10 nm to 60 nm and constant radius of 14 nm. The ITRS road plan has led to geometrical settings and mesh design, and this important work has ultimately produced the required technology node and feature size [38]. With the help of extensive 3D simulations done in SILVACO TCAD (ATLAS Device Simulator version: atlas 5.22.1.R) tools, it is shown here that the presented device exhibits better performance than the other NCTs and CTs with silicon materials. The 3D cylindrical design has Radius mesh (R in µm), Angle mesh (A in degrees), and Length mesh (Z in µm) and five regions of Al_0.30Ga_0.60As (Semiconductor), SiO₂ (Insulator), Conductor (Metal), Conductor (Metal) and Conductor (Metal). The coordinates for the cylindrical structure involved three electrodes: Drain, Source, and Gate. The device parameters of the proposed device are noted in Table 3.

The Shockley-Read-Hall and AUGER recombination models were used to analyze recombination effects for high current densities. NEWTON and GUMMEL models were incorporated into equations with coupled and decoupled forms. This paper describes the simulation of the electrical characteristics of novel transistor JLFET with gate-all-around architecture using ATLAS 3-D device simulator for different channel materials such as Gallium Arsenide (GaAs), Indium Phosphide (InP), Gallium Nitride (GaN), Gallium Phosphide (GaP), Aluminium Gallium Arsenide Phosphide (AlGaAsP), Indium Gallium Arsenide Phosphide (InGaAsP), Aluminium Gallium Arsenide (AlGaAs) and their different compositions as Al_0.20Ga_0.80As and Al_0.30Ga_0.60As.

4.1. Properties of AlGaAs

AlGaAs has numerous uses in the semiconductor industry. Since it is almost lattice-matched with GaAs, it is utilized in heterostructures to enable the development of heterostructures with low mechanical stresses. Fermi-level pinning at the nanowire surface can be lessened by the AlGaAs shell [39]. It is also employed in GaAs-based heterostructure devices as a barrier material. For instance, electrons are confined to a GaAs region by the AlGaAs layer in a quantum well-infrared photodetector (QWIP). With the combination of gallium arsenide and aluminum, the semiconductor material Al_xGa_1-xAs has a larger bandgap than gallium arsenide but nearly the same lattice constant. It is an alloy between gallium arsenide and aluminum arsenide, which is indicated by the x in the formula, which is a value between 0 and 1. AlGaAs is a zincblende crystal with a bandgap that ranges from 2.16 eV (AlAs) to 1.42 eV (GaAs).

When x is less than 0.4, the bandgap is direct. One of the most significant alloy systems in terms of technology is the (Al_xGa_1-xAs) system, particularly when paired with gallium arsenide (GaAs). It is the foundation for single-barrier, quantum-well, and superlattice device topologies, significantly impacting high-speed electronic gadgets. Thus, having the constants n and k spanning a broad spectral range and over the concentration range of x = 0 to x = l would be crucial. Fundamental parameters and electrical characteristics of AlGaAs are explained in Table 4 and Table 5.

5. Results and Discussion

In this study, JLFET is a usually ON gated resistor, and due to the workfunction difference between the gate and silicon nanowire, the threshold voltage is positive. Figure 2 presents the simulated transfer characteristics of JLFET architecture with Al_0.30Ga_0.60As, III-V material for different channel lengths ranging from 10 nm to 60 nm, and P⁺ Polysilicon has been used to fulfill the requirement of high gate workfunction to achieve appropriate V_TH value. It can be observed here that the rapidness of the drain current against the gate voltage increases as the channel length decreases. The threshold voltage value decreased as the channel length decreased, as shown in Figure 3. These I_D-V_GS characteristics of the cylindrical gate-all-around Al_0.30Ga_0.60As channel-based JLFET have been plotted at V_DS = 0.01V, spanning a range of V_GS from -0.4 to 1.2 V. The threshold voltages for different channel lengths have been observed to be V_th = 0.71864309 V (at 10 nm), 0.92221857 V (at 20 nm), 0.95883678 V (at 30 nm), 0.9691365 V (at 40 nm), 0.97815102 V (at 50 nm) and 0.98420158 V (at 60 nm). The result shows that JLFET can be a potential candidate for ultra-low power applications. It is because, in JLFET, complete depletion can be easily achieved for the OFF state by controlling the work function of gate material, and for the ON state, high doping levels in the nanowire-type substrate support a high current drive [39].

JLFET behaves as the close relative of accumulation mode FET. In heavily doped silicon (about 10¹⁹ cm^-3), the bulk mobility of electrons is low (approximately 60-80 cm²V^-1s^-1) and can be increased by applying gate voltage. Academic research papers show that JLFET can achieve higher mobility and is currently derived in moderate accumulation mode compared to CTs. Coulomb Scattering can be reduced by screening ionized impurities by the accumulation of electrons. In JLFET, the electric field perpendicular to the current flow is significantly lower than CTs. In CTs, this electric field reduces the inversion channel mobility, but the lower electric field in JLFET and the absence of carrier scattering lead to a significant breakthrough in high current drive [40].

Figure 4 shows the plot of the electric field distribution versus the distance from the gate electrode along the nanowire for 10 nm and 40 nm Al_0.30Ga_0.60As channel-based JLFET. The electric field strength at a particular distance from the gate electrode is proportional to the voltage applied to the gate electrode. The electric field profile is a critical parameter for understanding the behavior of electrons in JLFET. The distribution of the electric field is an essential factor in analyzing any device's performance, and it depends on material properties, doping profiles, and the structure of that device. In AlGaAs JLFET, the electric field lines are more concentrated and sharply defined due to higher current mobility. AlGaAs JLFET is less diffused electric field distribution and more concentrated around the gate region, resulting in a more tightly controlled conduction process [41]. For a 10 nm device, the electric field is stronger with a steeper gradient near the surface of the nanowire. This stronger electric field forces the electrons to flow in the nanowire. The result shows that 10 nm JLFET is more current drive than 40 nm JLFET.

Figure 5 and Figure 6 show the 10 nm and 40 nm energy band diagrams Al_0.30Ga_0.60As channel-based JLFET. The energy band diagram consists of a conduction band and a valence band. The conduction band is empty at zero bias, and all the electrons occupy only the valence band. The energy levels of the valence and conduction bands shift after applying some external voltage. The result shows that at 40 nm JLFET, the conduction and valence bands are wider than 10 nm JLFET. Due to increasing channel length, the electrons are more tightly coupled with gate voltage. More energy is required for the current drive. In contrast, for 10 nm JLFET, both energy bands are narrower than 40 nm JLFET and are the higher current drive in 10 nm device architecture [42].

Figure 7 shows the electric potential distribution of 10 nm and 40 nm Al_0.30Ga_0.60As channel-based JLFET. Electric field distribution depends on various factors, including channel doping in the silicon substrate, gate oxide material, and gate-to-source voltage for 40 nm JLFET. There is a significant increase in electric potential energy from the source, and the drain ends with a deeper and broader dip near the gate electrode compared to 10 nm JLFET. The main reason is the forming of a more significant depletion layer, which results in a more significant reduction in electric potential in that region [43].

Figure 8 shows the 10 nm and 40 nm current flow lines Al_0.30Ga_0.60As channel-based JLFET. In AlGaAs-based JLFET, the current is influenced by drift and diffusion phenomena similar to silicon, but AlGaAs has a direct energy band gap, and the current flow lines are more focused and less spread out than silicon [44]. Because of the shorter channel length that approaches the steeper electric field and higher current density, the current flow lines in the 10 nm device are more concentrated. Enclosing carriers can improve their carrying characteristics but can also cause more dispersion and possible failure. Due to the larger channel length of the 40 nm device, current flow lines are more dispersed, which produces a more even electrical distribution.

Figure 9 shows the electron concentration of 10 nm and 40 nm Al_0.30Ga_0.60As channel-based JLFET. The electron concentration or carrier density is crucial to understand the electrical performance of any device. It can also be influenced by doping, intrinsic properties, and temperature. The electron concentration in AlGaAs JLFET is deeper and higher than silicon JLFET [45]. More significant doping levels and an improved electric field can typically lead to a larger electron concentration in a 10 nm device. It may result in higher leakage currents and make device control more difficult. However, the electron concentration is usually lower for 40 nm devices, but it is more evenly spread throughout the channel, resulting in stable operation. The longer channel makes better control over carrier concentration possible, lessening leakage currents' effect and enhancing device reliability.

Figure 10 shows the electron mobility of 10 nm and 40 nm Al_0.30Ga_0.60As channel-based JLFET. Due to high mobility and wider bandgaps, AlGaAs enable faster electron transport, higher drive currents, and enhanced electrostatic control than silicon devices [46,47]. Reduced scattering is usually associated with higher electron mobility because a shorter channel facilitates more effective carrier transport. Although the 40 nm device's mobility may be marginally less than that of the 10 nm device, it has advantages such as reduced scattering and more stable operating conditions.

Figure 11 illustrates the I_D-V_DS characteristics of the cylindrical gate-all-around Al_0.30Ga_0.60As channel based JLFET at V_GS = 1.2 V, while V_DS ranges from 0 to 1 V. This device demonstrates a high ON-state current and a low OFF-state current, showcasing excellent electrostatic control, with a maximum drain current of 2.38548734 × 10^-5 A (at 10 nm), 1.31566809 × 10^-5 A (at 20 nm), 9.77385934 × 10^-6 A (at 30 nm), 8.5672922 × 10^-6 A (at 40 nm), 8.33677822 × 10^-6 A (at 50 nm) and 8.16522822 × 10^-6 A (at 60 nm) and saturation slope is about to 4.8060692 × 10^-6 A (at 10 nm), 2.1114994 ×10^-6 A (at 20 nm), 8.447915 ×10^-7 A (at 30 nm), 4.629001 ×10^-7 A (at 40 nm), 4.1971784 ×10^-7 A (50 nm) and 3.1932996 ×10^-7 A (60 nm). It can be understood here that the maximum drain current and saturation slope increase as channel length decreases.

Compared to other inversion devices, SCEs are less common in JLFETs. Equation 1 explains how the space charge area connected to the junctions (designated as SCE in the equation) and the expansion of the drain space charge region with drain voltage (designated as DIBL in the equation) cause the threshold voltage to decrease in the junction or other CT devices.

$$\mathbf{V}\mathbf{t}\mathbf{h}=\mathbf{V}\mathbf{t}\mathbf{h}\mathbf{o}-\mathbf{S}\mathbf{C}\mathbf{E}-\mathbf{D}\mathbf{I}\mathbf{B}\mathbf{L},$$

(1) 

Compared to other inversion devices, SCEs are less common in JLFETs. Equation 1 explains how the space charge area connected to the junctions (designated as SCE in the equation) and the expansion of the drain space charge region with drain voltage (designated as DIBL in the equation) cause the threshold voltage to decrease in the junction or other CT devices.

In CTs, in most cases, LSCE < Leff, where physical gate length is Lphysical, effective gate length is Leff when the device is in ON condition, and effective gate length is LSCE when the device is in OFF condition. In the JLFET case, electrostatic squeezing of the channel propagates into the source and drains in OFF condition, concluding the result as Leff > Lphysical, improving SCEs. In the ON condition, the "squeezing" phenomenon does not occur; hence, Leff = Lphysical. JLFETs are less subject to SCEs and have an excellent subthreshold slope and DIBL because doping concentration throughout the device length is constant. Mathematical expressions for subthreshold slope (SS) and drain-induced barrier lowering (DIBL) are explained in equations 2 and 3, respectively:

$$\mathrm{S}\mathrm{u}\mathrm{b}\mathrm{t}\mathrm{h}\mathrm{r}\mathrm{e}\mathrm{s}\mathrm{h}\mathrm{o}\mathrm{l}\mathrm{d} \mathrm{S}\mathrm{l}\mathrm{o}\mathrm{p}\mathrm{e}={\displaystyle \frac{\mathrm{d}{\mathrm{V}}_{\mathrm{G}}}{\mathrm{d}\mathrm{l}\mathrm{o}\mathrm{g}{\mathrm{I}}_{\mathrm{D}}}}$$

(2)

$$DIBL=V_{\begin{array}{c}TH@Vds=50mV \\ \\ \end{array}}-V_{TH@Vds=1V}$$

(3)

The simulated results for DIBL and SS versus different channel lengths for Al_0.30Ga_0.60As channel-based JLFET are plotted in Figure 12. The result shows that in JLFET, the high electric field region is placed in the drain, and the gate covers the outer side of this region. The impact of the drain electric field on the channel is much lower than that of CTs, which provide smaller DIBL. Under the threshold, the strongly doped JLFET depletion produces a large electric field perpendicular to the current flow; the field becomes zero above the threshold. A decrease in DIBL characterizes the OFF situation because the drain-source voltage drop does not occur in the channel region, and the blocking of the current is caused by squeezing the carriers out of the channel region [48].

Furthermore, the conduction mechanism in gate-all-around, Al_0.30Ga_0.60As channel-based JLFET, is compared with different channel lengths in Figure 13. Figure 13 depicts simulated results for I_ON and I_OFF versus different channel lengths. Moreover, results show that our design boasts some desirable features of JLFET, such as low leakage current and linear variation of drain current with control gate voltage. This device can be an ON & OFF switch in ultra-low power applications. In the ON condition of this device, the large current flows due to the heavily doped source and drain, but in the OFF state, the device cut off due to the work function difference between the gate material and silicon substrate [49].

Figure 14 illustrates the channel length dependency of the transconductance of cylindrical gate-all-around, Al_0.30Ga_0.60As channel-based JLFET for different channel lengths ranging from 10 nm to 60 nm. Having superior transconductance in JLFET architecture is attributed to its better charge transport properties than other CTs and NCTs. It can be observed here that the value of transconductance increases as channel length increases. Figure 14 illustrates the transconductance profile of Al_0.30Ga_0.60As channel-based JLFET for different channel lengths and simulation results showing a peak transconductance (gm) value of 1.3 × 10^-4 Siemens for 60 nm. The transconductance can be defined as the change in the drain current for change in the gate voltage and can be expressed as the ratio of the gate capacitance to the carrier transit time τ so that G=1/2πfτ.

The current-to-voltage ratio is commonly referred to as gain. The transconductance versus gate voltage graph shows the relationship between the device's transconductance and gate voltage with constant drain to source voltage and represents any device's amplification capability [50,51]. Transconductance and MOSFET threshold voltage (V_TH) are closely correlated and depend on gate channel size. Figure 14 demonstrates that the transconductance curve begins at a comparatively low value of g_m for a channel length of 10 nm, indicating modest amplification.

On the other hand, the g_m curve climbs steeply for longer channel lengths and increases amplification as the gate voltage increases. The gate voltage at which the derivative of low drain voltage transconductance, dg_m/dV_GS (g_m2), is highest is known as the threshold voltage. Moreover, JLFET with 60 nm channel length has the highest threshold voltage and transconductance.

5.1. Comparative Study of Subthreshold Analysis of JLFET with Different III-V Materials

This paper presents the DC analysis of cylindrical gate-all-around Al_0.30Ga_0.60As channel-based JLFET investigations with different channel lengths. Table 6 compares the suggested architectures with gate lengths ranging from 10 nm to 60 nm concerning gate length, threshold voltage, maximum drain current, saturation slope, subthreshold slope, DIBL, on current, and off current. The results indicate that the 10 nm device has the lowest threshold voltages, the highest maximum drain current, and a current and saturation slope. This work shows that the subthreshold slope of JLFETs with channel lengths of 40, 50, and 60 nm are approximately 47 mV/V, 45 mV/V, and 40 mV/V. JLFETs have the superior SS and DIBL and are less susceptible to SCEs due to constant doping concentration across the device length. Because the smaller SS demonstrated in this research lowers the OFF current of the transistor, it may be used in low-power applications. Our constructed JLFETs showed the lowest DIBL and SS values, indicating enhanced resilience against short-channel effects. The slope of the gate voltage to the drain current log is known as the SS. It is a crucial parameter for any device's subthreshold analysis. The findings demonstrate that the SS and DIBL values for the suggested task are in good agreement.

In this work, the subthreshold analysis of 40 nm cylindrical gate-all-around JLFET with various III-V channel materials has been provided and compared. Table 7 is furnished with 40 nm gate length, threshold voltage, maximum drain current, saturation slope, subthreshold slope, DIBL, on current and off current of the proposed structures having silicon as channel material and various channel materials for comparison. The different channel materials as Gallium Arsenide (GaAs), Indium Phosphide (InP), Gallium Nitride (GaN), Gallium Phosphide (GaP), Aluminium Gallium Arsenide Phosphide (AlGaAsP), Indium Gallium Arsenide Phosphide (InGaAsP), Aluminium Gallium Arsenide (AlGaAs) and their different compositions as Al_0.20Ga_0.80As and Al_0.30Ga_0.60As have been utilized in this work. The result shows that GaAs, Al_0.20Ga_0.80As, and Al_0.20Ga_0.80As devices have the highest I_on/I_off about 1.133861×1010, 4.299456 ×1012, and 6.942438 ×1013 and they also have maximum drain current, and saturation slope with lowest threshold voltages. Materials GaAs and AlGaAs have DIBL of about 30 mV/dec and SS value of about 64 mV/V. Other materials like Al_0.20Ga_0.80As and Al_0.30Ga_0.60As, GaP have DIBL about 28 mV/dec, 25 mV/dec, and 22 mV/dec, respectively. GaAs and their compound materials have provided good agreement of the values of SS and DIBL for proposed work with a subthreshold slope of about 63 mV/V, which is very close to the ideal value of 60 mV/V.

In Table 8, we have finally performed a performance comparison between our device and those available architectures in the literature. Materials, gate length, subthreshold slope, DIBL, on current, off current, and the ratio of on current to off current are provided in Table 8. Because of their direct energy band gap, better mobility compared to silicon, and superior subthreshold slope and DIBL, JLFETs made of III-V materials are less susceptible to SCEs. III-V material can have high frequency and speed due to its smaller SS. Our constructed JLFETs showed the lowest DIBL and SS values, indicating enhanced resilience against short-channel effects. The findings demonstrate that the SS and DIBL values for the suggested task are in good agreement.