An Investigation into Challenges of a 1-MHz, 1-kW Buck Converter

1. Introduction

Power electronic converters have become an integral part of various applications including aerospace [1], electric ships [2], and electric vehicles [3]. In these applications there is an emphasis in reducing the weight and footprint resulting in power dense, low-profile, and highly efficient power converters. To meet these stringent requirements switching frequencies are being pushed into the megahertz range [4]. This shift toward higher frequencies is driven by the need to reduce the size and weight of passive components, particularly inductors and transformers which play a central role in achieving high power density. However, despite the benefits of higher frequencies, magnetic components remain bottlenecks in the pursuit for further improvements [5]. Higher frequencies can reduce passive component size but pose challenges such as semiconductor reliability [6], thermal management, complex high frequency magnetics design [7], and managing electromagnetic interference (EMI) [8].

The advancement of wide-bandgap semiconductors has profoundly influenced converter design paradigms by enabling operation at higher switching frequencies [9]. A significant challenge, however, lies in the fluctuation of drain to source on-resistance $R_{\mathrm{DS},\mathrm{ON}}$, in Gallium Nitride (GaN) devices under varying operational conditions [10]. Traditionally the conduction loss estimation for thermal designs of these devices has relied on $R_{\mathrm{DS},\mathrm{ON}}$ values provided in datasheets. This static approach often falls short when these devices are operating in harsh environments [11]. As switching frequencies extend into the MHz range and power levels reach the kilowatt scale accurately predicting the junction temperature ($T_j$) becomes more complex and failure to do so can result in device degradation or catastrophic failure [12]. Various researchers have addressed this issue recently and proposed different methods to measure dynamic on-resistance $d{R}_{\mathrm{DS},\mathrm{ON}}$, in GaN devices. These previous methods are either application specific or complex and not efficient for MHz converters. For instance, a full-profile on-chip $R_{\mathrm{DS},\mathrm{ON}}$ measurement method has been proposed [13]. This method is specific to the designed chip and cannot be applied to other applications. Additionally, a physics-based SPICE model for p-GaN has been developed utilizing supplementary circuitry comprising diodes and resistors [14]. While this approach can be effective in low-frequency, low-power applications, parasitic effects contributed by PCB traces in the additional circuitry can impair GaN performance at MHz frequencies and higher power. Another method involving soft-switching topologies has been proposed. It similarly relies on additional components [15]. Therefore, this work aims to present a simplified and general applicable methodology to determine the change in $R_{\mathrm{DS},\mathrm{ON}}$ in MHz converters, thereby improving thermal design and enhancing system reliability without additional components or complexity.

Beyond semiconductor reliability, magnetic design is another critical factor in achieving high power densities. PCB-based magnetics have gained popularity in MHz power converter designs due to their ease of manufacturing and consistent quality [16]. However, despite the advantages PCB-based magnetics introduce significant challenges, particularly in terms of mitigating parasitic capacitances that are inherent to multi-layer PCB structures. These parasitics capacitances contribute to EMI and can degrade converter performance at higher power and frequency levels [17].

A 1-MHz PCB-based inductor was presented and analyzed for 200 W of power [18]. While the tested power and voltage were relatively low, parasitic effects which become more significant at higher frequencies and power levels were observed. Design guidelines for reducing parasitic capacitance in PCB-based inductors have been proposed [19]. This study did not specify key operating parameters such as the operating frequency and power levels, limiting its applicability to high power and MHz range applications. In another study, a PCB-based coupled inductor was tested at switching frequencies between 200-500 kHz in a $1.8$ buck converter [20]. However, parasitic effects were not a focus of this work leaving a gap in the understanding of how these issues impact performance in high power designs. Similarly, a planar inductor designed for a 300 , $2.7$ resonant converter was explored but the study did not specifically address parasitic behavior [21]. As the literature demonstrates PCB-based inductors are becoming prevalent in high power and high frequency applications. There is a clear need for further characterization of parasitic effects in these designs as they scale to higher frequencies and power densities where EMI mitigation becomes increasingly critical.

Another major challenge often overlooked in MHz designs is EMI which becomes increasingly significant as both the frequency and power levels in the converter rise [22]. EMI in power converters is categorized into two primary types: conducted and radiated [23]. Conducted EMI is further subdivided into differential mode (DM) and common mode (CM) noise [24]. Both DM and CM noise travel through the main power lines and distort the signal waveforms. CM noise couples through the parasitic capacitance via the chassis ground of the converter unit and flows back to the converter. In contrast, the primary sources of radiated EMI are high ${\displaystyle \frac{di}{dt}}$ current loops and high ${\displaystyle \frac{dv}{dt}}$ nodes [25].

The root causes of both conducted and radiated EMI can often be traced back to PCB parasitics in the layout due to large critical loop areas. Poorly designed layout for critical loops in high-frequency circuits creates parasitic inductances. These inductances cause voltage and current overshoots and are a major source of EMI [26]. While many studies have focused on high power density designs using wide bandgap devices, discussions of EMI mitigation typically remain confined to lower frequencies usually in the kilohertz range. For example, a behavioral model to predict CM emissions in a three-phase inverter switching at 500 kHz has been discussed [27]. Similarly, noise spectrum and radiated EMI in a flyback converter operating at 450 kHz were investigated [28]. A single-phase power factor correction boost converter was studied for conducted EMI at a frequency of 250 kHz [29]. Additionally, an EMI filter design method was proposed for a boost power factor correction prototype operating at 65 kHz [30] and conducted EMI simulations along with hardware tests were carried out for a buck converter operating at 100 kHz [31]. This study identified that the existing EMI study in literature focuses either on kHz range frequencies or on a single type of EMI, conducted or radiated in a particular converter. Therefore, this research aims to fill this gap by investigating the MHz frequency and impact of both conducted and radiated EMI.

Figure 1 provides a visual representation of the key areas addressed in this paper, where Figure 1a illustrates the converter used in the study. It shows the GaN HEMT device and the thermal network used to establish the relationship between $R_{\mathrm{DS},\mathrm{ON}}$ and $T_j$. It also highlights the loop inductances $L_p$, which are a major source of voltage and current overshoot/ringing and EMI. Furthermore, Figure 1b,c depict the parasitic effects in the inductor and the EMI spectrum of the converter, respectively.

The contributions of this work build upon these aspects, offering practical insights for addressing the challenges shown in Fig. 1. These are,

• A linear fit equation is proposed to accurately quantify the dynamic on-resistance of GaN HEMT device in relation to both losses and $T_j$.
• Characterization of a PCB-based inductor designed for a 1-MHz, 1-kW application with emphasis on core material selection and the minimization of parasitic effects, and
• conducted and radiated EMI tests for a MHz converter were performed and include both simulation and hardware results.

The rest of this paper is organized as follows. Section 2 provide details on the methodology developed to calculate the $R_{\mathrm{DS},\mathrm{ON}}$ of GaN device including the relationship between device losses and $T_j$. Section 3 examines the design of the PCB-based inductor focusing on core material selection and PCB winding parasitic followed by simulation and hardware results for a 1-MHz, 1-kW buck converter. In Section 4 a detailed analysis of EMI is provided. Finite Element Analysis (FEA) and electrical tools are used to simulate conducted EMI while radiated EMI is measured through on the developed hardware.

2. GaN HEMT Dynamic On-Resistance ($d{R}_{\mathrm{DS},\mathrm{ON}}$)

In power converters both conduction and switching losses are key factors affecting the temperature of the switching component [32]. The conduction loss primarily depends on the $R_{\mathrm{DS},\mathrm{ON}}$ of the device. This resistance tends to increase during operation due to several factors including charge trapping during high-voltage off-state biasing caused by the electric field, electron-induced charge trapping during hard-switching and a rise in the $T_j$ [33]. An increase in $R_{\mathrm{DS},\mathrm{ON}}$ leads to higher conduction losses in switching devices which in turn raises the $T_j$ of the switches. The switching devices in the MHz range switche many-times faster than in the kHz. This leads to more stress on the device and could be a reason for faster degradation. Therefore, understanding the behavior of $R_{\mathrm{DS},\mathrm{ON}}$ is crucial for achieving efficient thermal management and reliability of these devices in MHz converters.

2.1. Methodology

Direct measurement of $R_{\mathrm{DS},\mathrm{ON}}$ provides an accurate assessment of the device conduction losses which are essential for improving efficiency and ensuring effective thermal management. It also offers real-time insights into the device behavior under varying conditions reducing reliance on estimations or models. However, this approach requires additional circuitry which becomes increasingly complex at higher power and frequency levels [15]. As a result it is common practice to rely on indirect methods using manufacturer-provided datasheets. These datasheets typically present a normalized relationship between $R_{\mathrm{DS},\mathrm{ON}}$ and $T_j$ derived from data-driven processes during manufacturing. However, relying solely on nominal resistance values without accounting for dynamic changes under varying load profiles can introduce inaccuracies in loss calculations. This can also lead to improperly sized heatsinks, either oversized or undersized, reducing power density and compromising the device reliability.

Therefore, in this paper a linear equation was developed using the normalized curve for $R_{\mathrm{DS},\mathrm{ON}}$ provided by the manufacturer to calculate the normalized on-state resistance $R_{\mathrm{DS},\mathrm{ON}\left(\mathrm{norm}\right)}$, based on the junction temperature $T_j$, as

$$R_{\mathrm{DS},\mathrm{ON}\left(\mathrm{norm}\right)}=a{T}_j+b,$$

(1)

where a and b represent polynomial best-fit constants. After finding the $R_{\mathrm{DS},\mathrm{ON}\left(\mathrm{norm}\right)}$, the operational calculated on-state resistance $R_{\mathrm{DS},\mathrm{ON}\left(\mathrm{calc}\right)}$, is given as

$$R_{\mathrm{DS},\mathrm{ON}\left(\mathrm{calc}\right)}=R_{\mathrm{DS},\mathrm{ON}\left(\mathrm{manu}\right)}{R}_{\mathrm{DS},\mathrm{ON}\left(\mathrm{norm}\right)},$$

(2)

where $R_{\mathrm{DS},\mathrm{ON}\left(\mathrm{manu}\right)}$ is the value provided in the datasheet by manufacturer. Experimental measurement of $T_j$ is challenging in a packaged die; therefore, a thermal model should be used to calculate the $T_j$. The $T_j$ of power switching devices depends on the total power losses. These losses are switching losses $P_{\mathrm{sw}}$, and conduction losses $P_{\mathrm{cond}}$.

After calculating the total losses, a Cauer thermal network is used to estimate the temperature behavior. The thermal network of the switch is illustrated in Figure 1a. $T_c$ signifies the case temperature, $T_s$ represents the heat sink temperature, and $T_a$ corresponds to the ambient temperature. The thermal resistances include, from junction to case $R_{jc}$, from case to heat sink $R_{cs}$, and from heat sink to ambient $R_{sa}$. More details on losses and thermal network model can be found in [34]. From the thermal network, $T_j$ can be calculated as

$$T_j=P_{\mathrm{loss}}{R}_{jc}+T_c.$$

(3)

As the device operational lifetime decreases, $R_{\mathrm{DS},\mathrm{ON}}$ progressively increases. To further investigate the $d{R}_{\mathrm{DS},\mathrm{ON}}$ model, a special case study has been conducted where converter operates beyond-nominal design specs.

2.2. Experimental Results

A buck converter operating at 1-MHz is utilized. The hardware test bench is shown in Figure 2. It incorporates a 900-V GaN HEMT (TP90H050WS), a SiC Schottky diode (C4D08120A) and a PCB-based inductor [4]. The converter PCB was designed for a maximum current rating of 6.5 A and nominal operation of 5.5 A. The converter was tested up to 30% above the nominal current rating and the GaN device was closely monitored for changes in device characteristics. Since temperature is a major cause of failure, the temperature of components in the converter were monitored. The load profile changes in steps with each step change occurring after a steady-state wait time was observed.

Figure 3a illustrates the $R_{\mathrm{DS},\mathrm{ON}}$, $T_j$, and load in per unit (PU). In this context, 1 PU represents the nominal operating condition of the converter. On left y-axis a value of 1 signifies the nominal on-resistance value. The on-resistance during converter operation at varying loads was calculated and subsequently normalized against the on-resistance value specified in the manufacturer datasheet. The plot clearly shows that $R_{\mathrm{DS},\mathrm{ON}}$ increases with rising load. At a load 30% above the nominal operating point $R_{\mathrm{DS},\mathrm{ON}}$ increases by nearly 47%. The $T_j$ of the GaN device obtained form the thermal network reaches ${85}^{\circ }\mathrm{C}$.

Figure 3b illustrates the GaN HEMT losses and the discrepancy in error comparing on-resistance values from the datasheet against those derived using the aforementioned method. It highlights a rise in GaN losses attributed to an increase in on-resistance when subjected to beyond-nominal load conditions. It also illustrates the error percentage with losses differing by 5% at nominal load and nearing 8% at beyond-nominal load. The error percentage at any loading point can be calculated as

$$\%\mathrm{Error}=\left|{\displaystyle \frac{P_{\mathrm{loss}}\left(R_{\mathrm{DS},\mathrm{ON}\left(\mathrm{calc}\right)}\right)-P_{\mathrm{loss}}\left(R_{\mathrm{DS},\mathrm{ON}\left(\mathrm{manu}\right)}\right)}{P_{\mathrm{loss}}\left(R_{\mathrm{DS},\mathrm{ON}\left(\mathrm{manu}\right)}\right)}}\right|\times 100\%.$$

(4)

Such disparities in losses could significantly accelerate degradation in switching devices. Relying solely on data sheet values for static on-state resistance in thermal and loss calculations can lead to inaccuracies in understanding the true performance under various conditions especially in larger systems.

The thermal image of GaN HEMT taken during the experiment is illustrated in Figure 4. The switching device reached a maximum temperatures of ${69}^{\circ }\mathrm{C}$ at beyond-nominal loads. This is treated as case temperature. The $T_j$ will be more than the case as stated and shown in Figure 3.

3. PCB-Based Inductor

This section outlines the core material selection and inductor design specifications. It also discusses the inductor parasitic capacitance and characterization supported by both simulation and experimental results.

3.1. Core Material and Design Specs

Core materials composed of Manganese Zinc (MnZn) or Nickel Zinc (NiZn) exhibit properties suitable for operation within higher frequency range typically spanning from kilohertz to few megahertz. Magnetic materials such as 3F36 are well-suited for frequencies below 1 MHz while alternatives such as 3F4 and 3F46 can effectively operate up to 3 MHz [35]. These core materials are suitable for their respective frequencies but they still have room for improvement in terms of saturation flux density $B_{\mathrm{sat}}$, permeability $\mu$, losses at MHz range frequencies. Ferrite material 3F4 was chosen due to low power loss characteristics at nominal operating frequency for this design and the availability of selected core shape and size in the market.

Table 1 summarize the PCB-based inductor design specifications in Altium and FEA along with the designed converter parameters [4]. A square geometry was chosen for inductor as shown in Figure 5a, where $d_{\mathrm{out}}$ is the outer diameter, $d_{\mathrm{in}}$ is the inner diameter, s is the distance between two adjacent turns and w is the thickness of the trace width. Subsequently, a 2-layer PCB design was selected and the width of the copper traces on the PCB was determined based on the inductor current from the 1 MHz buck converter. To maintain a more compact design a PCB copper trace with a weight of 2 oz was chosen, enabling narrower trace width.

3.2. Parasitic Capacitance and Characterization

Despite the advantages of PCB-based magnetics they exhibit parasitic capacitance due to the large overlapping area and small spacing between layers. These parasitic capacitances can severely affect converter performance. These parasitic capacitances can resonate with inductance at high frequencies resulting in oscillations and these oscillations lead to voltage and current spike which are responsible for EMI [36]. In this design, all the inductor windings are placed on the top layer of the PCB to minimize the parasitic capacitances between layers. Placing inductor windings on a single layer such as the top layer of a PCB can help reduce parasitic capacitances between layers. When windings are distributed across multiple layers the proximity between the layers can create unwanted capacitances which degrades the performance of inductor particularly in high frequency designs. Keeping the windings on a single layer minimizes these interlayer interactions thereby reducing parasitic capacitance. However, the overall impact also depends on other factors such as PCB layout, trace spacing, and the dielectric properties of the PCB material.

Given the complexity of analytical methods, determining the parasitics of the inductor is typically done using FEA. The parasitic capacitances in the inductor are illustrated in Figure 5b where the turn-to-turn capacitance is represented as $C_{\mathrm{tt}}$, the turn-to-core capacitance as $C_{\mathrm{tc}}$, and the turn-to-ground capacitance as $C_{\mathrm{tg}}$. These three capacitances can be regarded as parallel connected capacitor $C_p$, as shown in Figure 5c [37]. Then the total capacitance $C_p$, as depicted in the equivalent model of the inductor will be sum of individual capacitances.

The PCB inductor was initially designed in Altium and subsequently imported into Q3D Extractor to determine its parasitic capacitance. Figure 5b illustrates the electric field distribution within the inductor demonstrating a uniform field. The total extracted parasitic capacitance of the inductor was found to be 3 $\mathrm{p}$$\mathrm{F}$. To validate the simulation results the extracted parasitics including equivalent series resistance (ESR) and parasitic capacitance were modeled in LTspice. Figure 6 presents an impedance sweep in LTspice incorporating the extracted parasitics and compares the results with hardware measurements. The realized inductor was characterized using an impedance analyzer (IM3570) and the results indicate a strong agreement between the impedance and phase from both simulation and hardware up to the 5 MHz limit of the impedance analyzer. Beyond 5 MHz resonance becomes evident in the simulation and the phase shifts toward $-{90}^{\circ }$ reflecting the increasing influence of capacitive effects at higher frequencies beyond 5 MHz. The fabricated inductor hardware shown in Figure 7a was tested in a 1-MHz, 1-kW buck converter. Figure 7b,c display the waveforms of the inductor current $I_L$, the drain-to-source voltage $V_{ds}$, and the thermal profile of inductor, respectively. The inductor reached a maximum temperature of ${70}^{\circ }\mathrm{C}$.

Once the critical design and testing phase of the converter is completed, the next step is to conduct testing for EMI measurement. This is to ensure that the converter does not interfere with other important systems in the surrounding. It also prepare the designers to make necessary adjustments in the design if there are any EMI issues.

4. Electromagnetic Interference (EMI)

This section presents analysis of both conducted and radiated EMI for the MHz converter. Conducted EMI analysis was carried out using FEA and electrical simulation tools while radiated EMI was tested on hardware. Although conducted EMI is significant, it can be effectively mitigated through the use of appropriate input filtering schemes and common mode chokes. For this reason, the focus of this paper is on radiated EMI as it poses a more substantial challenge at higher frequencies and power levels. Hardware testing was prioritized for radiated EMI as its mitigation requires more complex solutions beyond standard filtering techniques. Consequently, the results for conducted EMI are limited to simulations. The EMI results were evaluated in accordance with electromagnetic compliance (EMC) standards, specifically the International Special Committee on Radio Interference (CISPR) guidelines. CISPR 32 was applied to conducted EMI while radiated EMI testing followed CISPR 25/MIL-STD-461G standards [22].

4.1. Conducted EMI

The conducted EMI was analyzed using two approaches. First the PCB layout was designed and PCB parasitics such as inductance were extracted in FEA. These extracted parasitics were subsequently modeled in SIMPLIS. In SIMPLIS a Line Impedance Stabilization Network (LISN) model was developed to differentiate between DM and CM emissions. To visualize CM noise a small parasitic capacitance was introduced to mimic the capacitance from the heatsink to the chassis of the actual converter as a primary source of CM noise coupling. The LISN model was employed to simulate the electrical model of converter. Two scenarios were considered for the simulations: (1) without any input filter capacitor and (2) with an input filter capacitor.

Figure 8a–c presents the simulation results. As anticipated and as observed in Figure 8a,b, the absence of an input filter capacitor results in the highest levels of both DM and CM noise. It is evident that the addition of an input filter has significantly reduced both DM and CM noise. Thereby lowering the overall conducted emission in the converter.

The conducted EMI analysis of the designed PCB layout was also performed using FEA. Further details regarding the co-simulation design can be found in [38]. Figure 9 presents a comparison of the Fast Fourier Transform (FFT) plots for conducted emissions obtained from both the SIMPLIS and FEA simulations. These emissions are evaluated against CISPR 32 average measurement technique [39]. CISPR 32 defines two categories of products: Class A for industrial environments and Class B for residential environment with Class B imposing more stringent limits than Class A. The simulation results show that some noise components exceed the CISPR 32 Class B limit within the frequency range of 1 MHz to 5 MHz. However, the FEA simulation for the designed layout passed the CLASS B limit. Additionally, it is evident that the simulation results for the MHz converter from both methods closely track the emission trends across the frequency spectrum.

4.2. Radiated EMI

Radiated EMI testing was conducted in a laboratory environment. Ideally, such tests should be performed in open-area test sites if a semi-anechoic chamber is unavailable [40]. Radiated emissions measurements can also be conducted at various alternative sites including radio frequency absorber-lined metal chambers with conductive flooring or in large office and factory buildings where reflections do not interfere with the measurements.

However, due to the logistical challenges of transporting high-voltage equipment outdoor testing was not feasible. As a result three distinct locations ($Lo{c}_1$, $Lo{c}_2$, $Lo{c}_3$) were chosen for radiated EMI measurements following the guidelines in [40]. $Lo{c}_1$ was a power research laboratory with furniture, desktop computers, oscilloscopes and small bench power supplies in the surrounding area. $Lo{c}_2$ was a small electronics laboratory equipped with furniture, small bench power supplies and oscilloscopes. $Lo{c}_3$ was another power research laboratory containing power converter racks, hardware-in-the-loop machines and similar equipment. At each location four measurements were taken for each power level (100 W, 200 W, 300 W, 400 W). The CISPR 25 and MIL-STD-461G standard specifically addressing the low-frequency range of 150 kHz to 30 MHz was followed for this testing [22].

The H-800 SkyMatch antenna with a frequency range of 10 kHz to 50 MHz was used to measure the radiated emissions from the converter [41]. The R&S FSW 43 signal and spectrum analyzer operating from 2 Hz to 43.5 GHz was used for spectrum visualization [42]. During testing the antenna was positioned at four different orthogonal orientations (A, B, C, D) surrounding the device to capture varying emission profiles at a distance of 1 meter from the device under test (DUT) as shown in Figure 10. Measurements were taken at four power levels: 100 W, 200 W, 300 W, and 400 W at a switching frequency of 1 MHz across the three selected locations. To account for ambient noise an initial measurement was conducted with all power supplies and electronic loads turned on. Subsequently, the power levels were incrementally increased and emissions were recorded at each level.

Figure 11a illustrates the ambient noise levels recorded at three different locations. The remaining graphs, Figure 11b–d were generated as follows: for instance, at $Lo{c}_1$ with power level of 100 W, four measurements were taken at four different orthogonal antenna positions. The final graph for 100 W at $Lo{c}_1$ represents the average of these four measurements. This procedure was consistently applied for all power levels across the three locations. The radiated EMI results were compared against CISPR 25 Class 3 and Class 5 limits. Class 3 is typically used for general automotive applications whereas Class 5 imposes strict limits and is employed in environments where critical communication systems, such as radars and naval ships are present. As observed, the noise levels at $Lo{c}_1$ and $Lo{c}_3$ generally comply with the CISPR 25 Class 5 limit, except at a few frequencies where noise exceed the limit. In contrast, the noise levels at $Lo{c}_2$, particularly in the frequency range of 13 MHz to 27 MHz appear to exceed the limit. This could be attributed to the slightly higher ambient noise level at $Lo{c}_2$ as shown in Figure 11a. It may also result from the location proximity to electronic devices, power lines, or other radio frequency equipment. Additionally, $Lo{c}_3$ meets the Class 3 limit while $Lo{c}_1$ exhibits few noise content above this limit specifically at 22 MHz. It is important to note that the ambient noise levels have not been subtracted from the results presented in Figure 11b–d.

5. Conclusions

This paper addressed the challenges associated with high switching frequency converters focusing on three key areas: the variation of GaN HEMT $R_{\mathrm{DS},\mathrm{ON}}$, PCB-based inductor, and EMI. A simple linear equation was developed to calculate the change in $R_{\mathrm{DS},\mathrm{ON}}$ of GaN devices as a function of losses and $T_j$ . The model was applied in a case study where the converter PCB operated beyond its nominal design specifications, revealing a 47% increase in $R_{\mathrm{DS},\mathrm{ON}}$ when the load exceeded the nominal value by 30%. The parasitic capacitance of the PCB-based inductor was investigated through FEA and compared with hardware measurements. Key factors influencing parasitic capacitance, including PCB layers, winding thickness, inter-layer spacing and material permeability were identified. Additionally, conducted EMI was analyzed using FEA and electrical simulation tools highlighting the significant role of input filtering in mitigating conducted EMI. Radiated EMI tests were performed at three different locations and compared against CISPR 25 standards. It was observed that $Lo{c}_2$ exhibited higher spectral interference primarily due to surrounding noise as confirmed by ambient measurements. These EMI results offer valuable insights into the design of high-power dense converters in terms of their potential to pass EMC tests. The methodology discussed in this paper provides a framework for assessing a product emissions profile prior to mass production, allowing for necessary modifications to ensure compliance with EMC standards.