Submitted:
19 July 2024
Posted:
20 July 2024
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Abstract
Keywords:
1. Introduction
2. Theoretical Analysis
- Class E with infinite DC Feed: is a more idealized model where the DC feed inductance is assumed to be infinite. In practice, this means that the inductance is large compared to other reactance’s in the circuit. This configuration simplifies the theoretical analysis of the amplifier and can lead to idealized performance predictions, such as very high efficiency. However, in practical applications, achieving truly 'infinite' inductance is impossible, so this model serves more as a theoretical benchmark or a design starting point.
- b. Class E with finite DC Feed: here the DC feed inductance is finite, meaning it has a specific, non-infinite value. This configuration is more practical and commonly used in real-world applications. The finite DC feed provides a certain level of control over the amplifier's operation, including aspects like the RF waveform shape and the amplifier's efficiency. However, the finite value of the inductance can introduce additional considerations in the design, such as the impact on bandwidth and stability.
2.1. Class E Load Network Topology with Infinite DC Feed
2.2. Class E Load Network Topology with Finite DC Feed
3. Quality Factor (Q) and It’s Trade-Offs
4. Design Methodology : Importance of Harmonic Termination
- Set the Design Frequency: Begin by specifying the frequency at which the design will operate. This is a critical first step that influences all subsequent parameters and choices.
- Determine Required Bias Voltage Levels: Identify the necessary bias voltage levels for the design. These levels are essential for ensuring the proper operation of the components within the design and the output power.
- Calculate Idealized Values: Compute the ideal values for the critical design parameters. These calculations will serve as a reference for the initial simulation and guide the optimization process.
- Run Initial Simulation: Input the idealized values obtained in step 3 into the simulation tool. The outcomes of this simulation should include suppression of the second harmonic and high efficiency at the design frequency.
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Optimize with Fixed Capacitance Co: Keeping the capacitance constant Co, conduct an optimization over a bandwidth of 20%, aiming for 4 specific goals to get the optimum values for R, L, C, L1, L2, L3, C2 and C3 once convergence is reached. The search is done within the range of [0.5 - 2] times the values of R, L, C while [0.5 - 3] times L1, L2, L3 , C2 and C3 from the theoretical values to get the best possible design.
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- The fundamental frequency should achieve the required power level.
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- The second and third harmonics should be suppressed to X dBc.
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- The second and third harmonics should be suppressed to X dBc. (required level)
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- The PAE must be at least PP % (PP is the targeted value)
- Adjust for Different Power Levels: If there is a need to optimize for a different power level, ensure to maintain the ratio of voltage to power constant. This approach preserves the similarity in optimum resistance R values across different power levels, facilitating a scalable design strategy.
- Finalize the Design: With the optimization complete, review the design parameters to ensure they meet the desired specifications. Adjustments can be made as necessary to fine-tune the design.
5. Results and Discussion
6. Conclusions and Future Work
Funding
Data Availability Statement
Conflicts of Interest
References
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| Var. | R | C | L | C0 | L1 | L2 | L3 | C2 | C3 |
| Units | Ω | pF | nH | pF | nH | nH | nH | pF | pF |
| 50 MHz | |||||||||
| Ideal | 136.50 | 15.97 | 318 | 22.72 | 167.17 | 208.96 | 53 | 12.12 | 21.22 |
| Opti. | 147.7 | 20 | 362 | 23 | 206 | 395 | 86 | 6 | 14 |
| 100 MHz | |||||||||
| Ideal | 136.50 | 7.98 | 159.02 | 11.36 | 83.58 | 104.48 | 26.52 | 6.06 | 10.61 |
| Opti. | 157.74 | 12 | 109 | 11 | 190 | 113 | 55 | 6 | 6 |

| Values- | R | C | L | Lx |
| Topology 1 | 57.68 Ω | 10.13 pF | - | 211.60 nH |
| Topology 2.1 | 63.50 Ω | 10.62 pF | 3.82 uH | 213.85 nH |
| Topology 2.2 | 136.50 Ω | 15.97 pF | 318.04 nH | - |
| Q (50 MHz) | PAE |
Fund. (dBm) |
2nd (dBm) |
3rd (dBm) |
| Topology 1: With DC feed | ||||
| 10 | 81.137 | 29.341 | 18.545 | 9.695 |
| 50 | 87.458 | 29.592 | 16.092 | 4.096 |
| 100 | 90.358 | 29.595 | 13.262 | -0.640 |
| 500 | 92.812 | 29.421 | 2.401 | -14.326 |
| 1000 | 92.896 | 29.370 | -3.220 | -20.309 |
| Topology 2.1: With finite DC feed and q = 0.5 | ||||
| 10 | 78.402 | 31.450 | 20.706 | 12.265 |
| 50 | 87.116 | 31.879 | 16.983 | 4.353 |
| 100 | 89.825 | 31.257 | 13.257 | -1.326 |
| 500 | 91.497 | 31.726 | 1.178 | -15.60 |
| 1000 | 91.561 | 31.690 | -4.620 | -21.655 |
| Topology 2.2: With finite DC feed and q = 1.412 | ||||
| 10 | 76.885 | 28.581 | 18.471 | 13.588 |
| 50 | 76.834 | 28.683 | 18.910 | 12.722 |
| 100 | 80.932 | 29.076 | 18.624 | 8.544 |
| 500 | 90.205 | 29.403 | 7.738 | -9.144 |
| 1000 | 92.711 | 29.349 | 1.504 | -16.058 |
| 1500 | 92.773 | 29.328 | -2.119 | -19.855 |
| Var. | R | C | L | C0 | L1 | L2 | L3 | C2 | C3 |
| Units | Ω | pF | nH | pF | nH | nH | nH | pF | pF |
| 50 MHz | |||||||||
| Ideal | 136.50 | 15.97 | 318 | 22.72 | 167.17 | 208.96 | 53 | 12.12 | 21.22 |
| Opti. | 147.7 | 20 | 362 | 23 | 206 | 395 | 86 | 6 | 14 |
| 100 MHz | |||||||||
| Ideal | 136.50 | 7.98 | 159.02 | 11.36 | 83.58 | 104.48 | 26.52 | 6.06 | 10.61 |
| Opti. | 157.74 | 12 | 109 | 11 | 190 | 113 | 55 | 6 | 6 |
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