PreprintArticleVersion 1Preserved in Portico This version is not peer-reviewed
A Comprehensive Research on Unclamped-Inductive-Switching (UIS)-Induced Electrical Parameters Degradations and Optimizations for 4H-SiC Trench MOSFETs Structures
Version 1
: Received: 13 May 2024 / Approved: 13 May 2024 / Online: 13 May 2024 (17:02:16 CEST)
How to cite:
Liu, L.; Guo, J.; Shi, Y.; Zeng, K.; Li, G. A Comprehensive Research on Unclamped-Inductive-Switching (UIS)-Induced Electrical Parameters Degradations and Optimizations for 4H-SiC Trench MOSFETs Structures. Preprints2024, 2024050880. https://doi.org/10.20944/preprints202405.0880.v1
Liu, L.; Guo, J.; Shi, Y.; Zeng, K.; Li, G. A Comprehensive Research on Unclamped-Inductive-Switching (UIS)-Induced Electrical Parameters Degradations and Optimizations for 4H-SiC Trench MOSFETs Structures. Preprints 2024, 2024050880. https://doi.org/10.20944/preprints202405.0880.v1
Liu, L.; Guo, J.; Shi, Y.; Zeng, K.; Li, G. A Comprehensive Research on Unclamped-Inductive-Switching (UIS)-Induced Electrical Parameters Degradations and Optimizations for 4H-SiC Trench MOSFETs Structures. Preprints2024, 2024050880. https://doi.org/10.20944/preprints202405.0880.v1
APA Style
Liu, L., Guo, J., Shi, Y., Zeng, K., & Li, G. (2024). A Comprehensive Research on Unclamped-Inductive-Switching (UIS)-Induced Electrical Parameters Degradations and Optimizations for 4H-SiC Trench MOSFETs Structures. Preprints. https://doi.org/10.20944/preprints202405.0880.v1
Chicago/Turabian Style
Liu, L., Kai Zeng and Gangpeng Li. 2024 "A Comprehensive Research on Unclamped-Inductive-Switching (UIS)-Induced Electrical Parameters Degradations and Optimizations for 4H-SiC Trench MOSFETs Structures" Preprints. https://doi.org/10.20944/preprints202405.0880.v1
Abstract
In this paper, single and repetitive frequency UIS characteristics of 1200 V asymmetric (AT)and double trench silicon carbide (DT-SiC) metal–oxide-semiconductor field-effect transistors (MOSFETs) under different working conditions are investigated by experiment and simulation. For asymmetric trench SiC MOSFETs, the failure mode is all thermal runaway under working conditions. However, the failure mode of double trench SiC MOSFETs mostly is gate oxide rupture, which indicates an instable avalanche robustness under UIS stress. The variations of measured parameters are recorded to evaluate typical electrical features of device failure. Furthermore, TCAD simulation is used to reveal the electro-thermal stress inside the device during avalanche. Additionally, failed devices are decapsulated to verify the location of failure point from the perspective of the semiconductor die. Finally, a new type of stepped-oxide vertical power DT MOSFET with P-type shielding and current spread layers is proposed for improvement of gate dielectric reliability.
Keywords
SiC Trench Power MOSFET; UIS; Failure analysis; Optimized structure
Subject
Engineering, Electrical and Electronic Engineering
Copyright:
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
