Preprint Article Version 1 Preserved in Portico This version is not peer-reviewed

Effect of Parasitic Channel on DC/AC/RF Characteristics and Power Consumption of GAA Si NS MOSFETs and Circuits

Version 1 : Received: 16 October 2023 / Approved: 16 October 2023 / Online: 16 October 2023 (09:53:47 CEST)

How to cite: Kola, S. R.; Li, Y. Effect of Parasitic Channel on DC/AC/RF Characteristics and Power Consumption of GAA Si NS MOSFETs and Circuits. Preprints 2023, 2023100958. https://doi.org/10.20944/preprints202310.0958.v1 Kola, S. R.; Li, Y. Effect of Parasitic Channel on DC/AC/RF Characteristics and Power Consumption of GAA Si NS MOSFETs and Circuits. Preprints 2023, 2023100958. https://doi.org/10.20944/preprints202310.0958.v1

Abstract

In this paper, we study the effect of parasitic channel on electrical characteristics and power consumptions of vertically stacked gate-all-around (GAA) silicon nanosheet (NS) MOSFETs of the bulk and silicon-on-insulator (SOI) substrates. Through deliberate control of the bottom parasitic channel coverage, we systematically assess its influence on DC, AC, and RF characteristics including power consumption. The observed findings highlight a significant differentiation among the bottom parasitic channels: GAA (i.e., control sample with 100% coverage), omega-shaped gate NS (70% and 80% coverages), and FinFET (60% coverage). Compared with the device with a 60% coverage channel, the device with a 100% coverage channel possesses 3520% and 8030% normalized leakage current improvement for both NFET and PFET under the bulk substrate, respectively. Compared with bulk-substrate devices, the SOI-substrate devices further significantly improve the leakage current. Due to enhanced off-state current leakages in the 100% covered bulk-substrate device, the static power demonstrates a notable improvement (about 98.1%), compared to 60% covered devices. Hence, the utilization of a 60% covered channel will result in a degradation of both device and circuit performance. The observation of GAA NS MOSFET indicates that an increase in the bottom parasitic channel coverage ratio leads to a positive impact on power consumption and leakage currents. The examination presented here is useful in the fabrication of stacked GAA NS MOSFETs.

Keywords

gate-all-around; nanosheet; silicon-on-insulator; vertically stacked; parasitic channel; short-channel effect; current densities; gate capacitances; transconductance; cut-off frequency; 3dB frequency; power consumption; 3-D device simulation

Subject

Engineering, Electrical and Electronic Engineering

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