Test Structures for the Characterization of the Gate Resistance in 16nm FinFET RF Transistors

1. Introduction

In the last two decades CMOS technologies have become mainstream not only for digital logic but also for RF and millimeter-wave applications. This was possible thanks to the continuous downscaling and layout optimization, which has allowed to reach values of $f_t$ and $f_{max}$ close to 400 $\mathrm{G}$$\mathrm{Hz}$[1,2]. The gate resistance $R_g$ is a key parasitic parameter for RF transistors, as it has a significant impact on $f_{max}$ and on the noise performance [3,4]. In order to keep $R_g$ low, circuit designers have to select a suitable geometry for the active devices [5], and to do so it is crucial that the behavior of $R_g$ be correctly captured in the compact models of the transistors. In the last years a lot of research work has been published on this topic, achieving very good results [6,7,8,9,10]. Since the target of any model is to reproduce measurement results as closely as possible, using the best-known measurement methodology is a fundamental pre-requisite. In the reviewed literature the standard common-source structure with open-short de-embedding is always used. In this article we consider also an alternative structure with the transistor connected in capacitor mode, called ”capacitor-like” structure, which requires only the open de-embedding step. The article is organized as follows: in Section 2 the main features of the two methodologies are presented along with a list of fabricated test structures. In Section 3 the capacitor-like structure is analyzed in detail and some design guidelines are derived to achieve accurate measurement results. In Section 4 the standard and capacitor-like structures are compared and finally in Section 5 the conclusions of this study are presented.

2. Standard and Capacitor-Like Structures—Description

The standard method is based on the structure in Figure 1, which consists of an RF transistor in common-source configuration routed to RF GSG pads. This is the structure which is commonly used to extract $R_g$ as well as the other equivalent-circuit parameters of the MOS transistor, and requires open and short structures to de-embed the pads and feedline parasitics. Using the small-signal equivalent circuit of the MOS transistor, the gate resistance can be extracted from the 2-port Y-parameters using the formula $R_g=Re(1/Y_{11})$[9], under the assumption that the source and drain parasitic resistances $R_s$ and $R_d$ are negligible with respect to $R_g$.

The alternative capacitor-like structure in Figure 2 features the RF transistor connected in capacitor-mode, namely with the gate connected to both input and output pads, and source and drain shorted to ground.

One key advantage of this structure is that it requires only the open de-embedding step. Indeed, once we remove the shunt parasitic components of the pads with the open de-embedding, we are left with a T-network formed by the feedlines and the DUT, as shown in Figure 3. Taking $Z_{21}$ of this network automatically excludes the contribution of the feedlines and no additional de-embedding step is required. Based on considerations very similar to those done for the standard structure, it is found that $R_g=Re\left(Z_{21}\right)$, again under the assumption that $R_s,R_d\ll R_g$. It should be noted that this concept can not be used in 1-port configuration, as it would require both the open and short de-embedding steps.

For this study 18 test structures utilizing both the standard and capacitor-like concept were fabricated in a 16nm FinFET process. All the structures use nmos RF transistors with the lowest threshold voltage ($V_t$) and differ in the number of fins ($N_{fins}$), gate length ($L_g$) and in the number of devices in parallel, the so-called multiplicity (M). The list of all the available test structures with the related geometrical features is presented in Table 1. In addition to several instances of the capacitor-like structure, three standard structures with different values of M (1,4,8) were fabricated as reference.

The 2-port S-parameters of the test structures were measured from DC to 110 $\mathrm{G}$$\mathrm{Hz}$ using a vector network analyzer (VNA) calibrated up to the probe tips. The on-chip interconnections are de-embedded up to the third level of metallization (M3).

In order to assess the quality of the measurement we utilized the relative deviation $\Delta R_g$ of the measured gate resistance ($R_{g,meas}$) from the one predicted by the foundry model ($R_{g,sim}$):

$$\Delta R_g=\frac{R_{g,meas}-R_{g,sim}}{R_{g,meas}}$$

(1)

It was verified that $R_{g,sim}$ follows the expected scaling law with respect to $N_{fins}$ and M [11], given by:

$$R_g=\frac{R_{conn}+R_{gv}/N_{fins}+R_{gl}\times N_{fins}}{M}$$

(2)

where $R_{gv}$ and $R_{gl}$ are respectively the vertical and lateral gate resistance components per fin and $R_{conn}$ is a constant which includes end resistances, contact resistances and interconnects up to M3. This result, shown in Figure 4, justifies the usage of the foundry model as reference to assess the quality of the measured data (Equation (1)).

3. Capacitor-Like Structures

This section focuses on the analysis of the capacitor-like structure. The plot of $R_g$ vs frequency in Figure 5 shows very good agreement with the foundry model over the entire frequency range for $V_g=0.4\mathrm{V}$, whereas the plots of $\Delta R_g$ over frequency for different bias conditions in Figure 6 show that the best agreement between measurement and simulation is obtained for $V_g=0.4\mathrm{V}$. The reason is that the gate resistance consists of a bias-independent contribution from the gate electrode $R_{g,el}$ and a bias-dependent contribution from the channel $R_{ch}\left(V_g\right)$[7,9,12]. In order to predict $R_{g,ch}\left(V_g\right)$ accurately, the device section including gate, oxide and channel should be modeled as a distributed RC network [6], which would result in additional complexity of the model and increased simulation time. In order to avoid this, many compact RF models embed the $R_{ch}$ contribution into the bias-independent $R_g$, assuming for $V_g$ the value which maximizes $f_t$ or $f_{max}$. This is exactly $V_g=0.4\mathrm{V}$ for this technology and transistor type, which explains why the best agreement between measurement and simulation is attained under this bias condition.

Table 2 reports the values of $\Delta R_g$ for different DUTs at $V_g=0.4\mathrm{V}$ and $f_0=50\mathrm{G}\mathrm{Hz}$, which is approximately in the middle of the analyzed frequency range. It can be observed that a minimum total device width is required to achieve good agreement between measurement and simulation. The reason is that for the smallest devices like DUT1, the total gate capacitance $C_{gg}$ of the transistor is smaller or comparable to the pad capacitance $C_{pad}\sim 25\mathrm{f}\mathrm{F}$, which results in a large numerical error in the open de-embedding step. This phenomenon can be also observed simulating the de-embedding process using an approach similar to that of [13]. Based on these considerations, a large value of M should be used if the width of the transistor is small.

Finally, in Figure 7 the measured $R_g$ is compared to simulations as a function of the geometrical parameters $N_{fins}$ and $L_g$, showing good correlation.

4. Comparison between Standard and Capacitor-Like Structures

In order to make an effective comparison between the two types of structure, standard DUTs 16, 17 and 18 have been included in the teschip, having the same active size as capacitor-like DUTs 4, 8 and 12 respectively. Comparing $\Delta R_g$ of the 3 pairs of structures, it is found that the standard structure gives the best results for $M=1$, as shown in Table 3. Larger values of M (4 and 8) lead to larger deviations and should be avoided. The capacitor-like structure instead is less sensitive on M for the unit device width at hand. All in all, the best achievable $\Delta R_g$ with the two structures is comparable.

The second important comparison criterion is the stability of the measured $R_g$ over frequency, which could be potentially influenced by the de-embedding structures. It can be quantified by means of the normalized standard deviation over frequency ${\widehat{\sigma }}_{R_g}/\overline{R_g}$, where $\overline{R_g}$ and ${\widehat{\sigma }}_{R_g}$ are respectively the mean value and the standard deviation of $R_g$ over frequency, defined as:

$$\overline{R_g}=\sum _{i=1}^N{R}_g\left(f_i\right)$$

(3)

$${\widehat{\sigma }}_{R_g}=\sqrt{\frac{1}{N}{\sum }_{i=1}^N{(R_g\left(f_i\right)-\overline{R_g})}^2}$$

(4)

with N being the number of frequency points. The normalized standard deviation is plotted in Figure 8 as a function of $V_g$ for the standard and capacitor-like structures with different values of M. It can be observed that the measurements performed with the two structures show similar stability over frequency, with the exception of $M=8$, for which the capacitor-like structure has lower variance at large $V_g$ values.

5. Conclusions

In this article, the standard and capacitor-like structures for the characterization of the gate resistance were analyzed and compared. It was found that the design guidelines to achieve best accuracy in the two types of structure are somehow opposite: for the standard structure there is a constraint on the maximum transistor size, whereas for the capacitor-lilke structure on the minimum size. The two methods show similar accuracy and similar variance over frequency.