Preprint Article Version 1 Preserved in Portico This version is not peer-reviewed

Tunneling Current Model under Drain Induced Barrier Lowing Effects for Scaled Devices

Version 1 : Received: 25 July 2022 / Approved: 26 July 2022 / Online: 26 July 2022 (09:37:33 CEST)

How to cite: Zhao, Z.; Wu, T.; Wang, M.; Xi, Y.; Feng, Q.; Sun, Y. Tunneling Current Model under Drain Induced Barrier Lowing Effects for Scaled Devices. Preprints 2022, 2022070398. https://doi.org/10.20944/preprints202207.0398.v1 Zhao, Z.; Wu, T.; Wang, M.; Xi, Y.; Feng, Q.; Sun, Y. Tunneling Current Model under Drain Induced Barrier Lowing Effects for Scaled Devices. Preprints 2022, 2022070398. https://doi.org/10.20944/preprints202207.0398.v1

Abstract

With the proportional reduction of MOSFET size, the leakage-to-barrier reduction (DIBL) effect leads to a more significant increase in the tunneling current on the gate, and the appearance of the gate tunneling current also seriously affects the static characteristics of the device. In this paper, a new theoretical model of the relationship between the direct tunneling current and the thickness of the oxide layer under the DIBL effect is proposed for the MOSFET device with ultra-thin oxide layer. On this basis, the characteristics of the MOSFET device are studied in detail by using HSPICE, and their working conditions are quantitatively analyzed. The characteristic variation trend of small-size devices under the influence of gate tunneling current is predicted. The simulation results using BSIM4 model are consistent with the theoretical model. The theory and data in this paper will provide useful reference for large scale integrated circuit design.

Keywords

Scaled device; Ultra-Thin gate oxide; DIBL; Direct tunneling current

Subject

Engineering, Electrical and Electronic Engineering

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