Preprint Article Version 1 Preserved in Portico This version is not peer-reviewed

Impact of Residual Stress on a Polysilicon Channel in Scaled 3D NAND Flash Memory

Version 1 : Received: 8 October 2021 / Approved: 19 October 2021 / Online: 19 October 2021 (10:12:01 CEST)
Version 2 : Received: 21 October 2021 / Approved: 21 October 2021 / Online: 21 October 2021 (12:12:18 CEST)

A peer-reviewed article of this Preprint also exists.

Lee, J.; Yoon, D.-G.; Sim, J.-M.; Song, Y.-H. Impact of Residual Stress on a Polysilicon Channel in Scaled 3D NAND Flash Memory. Electronics 2021, 10, 2632. Lee, J.; Yoon, D.-G.; Sim, J.-M.; Song, Y.-H. Impact of Residual Stress on a Polysilicon Channel in Scaled 3D NAND Flash Memory. Electronics 2021, 10, 2632.

Journal reference: Electronics 2021, 10, 2632
DOI: 10.3390/electronics10212632

Abstract

The effects of residual stress in a tungsten gate on a polysilicon channel in scaled 3D NAND flash memories were investigated using a technology computer-aided design simulation. The NAND strings with respect to the distance from the tungsten slit were also analyzed. The scaling of the spacer thickness and hole diameter induced compressive stress on the polysilicon channel. Moreover, the residual stress of polysilicon in the string near the tungsten slit had greater compressive stress than the string farther away. The increase in compressive stress in the polysilicon channel degraded the Bit-Line current (Ion) because of stress-induced electron mobility deterioration. Moreover, a threshold voltage shift (△Vth) occurred in the negative direction because of conduction band lowering.

Keywords

3D NAND; hole profile; mechanical stress; polysilicon channel; scaling; TCAD

Subject

ENGINEERING, Electrical & Electronic Engineering

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