Preprint Article Version 2 This version is not peer-reviewed

Towards Neuromorphic Learning Machines using Emerging Memory Devices with Brain-like Energy Efficiency

Version 1 : Received: 19 July 2018 / Approved: 19 July 2018 / Online: 19 July 2018 (14:39:39 CEST)
Version 2 : Received: 31 August 2018 / Approved: 6 September 2018 / Online: 6 September 2018 (10:53:42 CEST)

A peer-reviewed article of this Preprint also exists.

Saxena, V.; Wu, X.; Srivastava, I.; Zhu, K. Towards Neuromorphic Learning Machines Using Emerging Memory Devices with Brain-Like Energy Efficiency. J. Low Power Electron. Appl. 2018, 8, 34. Saxena, V.; Wu, X.; Srivastava, I.; Zhu, K. Towards Neuromorphic Learning Machines Using Emerging Memory Devices with Brain-Like Energy Efficiency. J. Low Power Electron. Appl. 2018, 8, 34.

Journal reference: J. Low Power Electron. Appl. 2018, 8, 34
DOI: 10.3390/jlpea8040034

Abstract

The ongoing revolution in Deep Learning is redefining the nature of computing that is driven by the increasing amount of pattern classification and cognitive tasks. Specialized digital hardware for deep learning still holds its predominance due to the flexibility offered by the software implementation and maturity of algorithms. However, it is being increasingly desired that cognitive computing occurs at the edge, i.e. on hand-held devices that are energy constrained, which is energy prohibitive when employing digital von Neumann architectures. Recent explorations in digital neuromorphic hardware have shown promise, but offer low neurosynaptic density needed for scaling to applications such as intelligent cognitive assistants (ICA). Large-scale integration of nanoscale emerging memory devices with Complementary Metal Oxide Semiconductor (CMOS) mixed-signal integrated circuits can herald a new generation of Neuromorphic computers that will transcend the von Neumann bottleneck for cognitive computing tasks. Such hybrid Neuromorphic System-on-a-chip (NeuSoC) architectures promise machine learning capability at chip-scale form factor, and several orders of magnitude improvement in energy efficiency. Practical demonstration of such architectures has been limited as performance of emerging memory devices falls short of the expected behavior from the idealized memristor-based analog synapses, or weights, and novel machine learning algorithms are needed to take advantage of the device behavior. In this work, we review the challenges involved and present a pathway to realize ultra-low-power mixed-signal NeuSoC, from device arrays and circuits to spike-based deep learning algorithms, with ‘brain-like’ energy-efficiency.

Subject Areas

Cognitive Computing; Deep Learning; Intelligent Cognitive Assistants (ICA); Neuromorphic System-on-a-Chip (NeuSoC); NVRAM; RRAM; Spiking Neural Networks (SNNs).

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