Preprint Article Version 1 This version is not peer-reviewed

Towards Neuromorphic Learning Machines using Emerging Memory Devices with Brain-like Energy Efficiency

Version 1 : Received: 19 July 2018 / Approved: 19 July 2018 / Online: 19 July 2018 (14:39:39 CEST)
Version 2 : Received: 31 August 2018 / Approved: 6 September 2018 / Online: 6 September 2018 (10:53:42 CEST)

How to cite: Saxena, V.; Wu, X.; Srivastava, I.; Zhu, K. Towards Neuromorphic Learning Machines using Emerging Memory Devices with Brain-like Energy Efficiency. Preprints 2018, 2018070362 (doi: 10.20944/preprints201807.0362.v1). Saxena, V.; Wu, X.; Srivastava, I.; Zhu, K. Towards Neuromorphic Learning Machines using Emerging Memory Devices with Brain-like Energy Efficiency. Preprints 2018, 2018070362 (doi: 10.20944/preprints201807.0362.v1).

Abstract

The ongoing revolution in Deep Learning is redefining the nature of computing that is driven by the increasing amount of pattern classification and cognitive tasks. Specialized digital hardware for deep learning still holds its predominance due to the flexibility offered by the software implementation and maturity of algorithms. However, it is being increasingly desired that cognitive computing occurs at the edge, i.e. on hand-held devices that are energy constrained, which is a energy prohibitive when employing digital von Neumann architectures. Recent explorations in digital neuromorphic hardware have shown promise, but offer low neurosynaptic density needed for scaling to applications such as intelligent cognitive assistants (ICA). Large-scale integration of CMOS mixed-signal integrated circuits and nanoscale emerging memory devices can enable a new generation of Neuromorphic computers that can alleviate the von Neumann bottleneck for cognitive computing tasks. Such hybrid Neuromorphic System-on-a-chip (NeuSoC) architectures promise machine learning capability at chip-scale form factors, and several orders of magnitude reduction in energy consumption. Practical demonstration of such architectures has been impeded as the performance of these emerging devices falls short of the expected behavior from the idealized analog synapses, or weights, and new learning algorithms are needed to take advantage of the device behavior. In this work, we discuss the challenges involved and present a pathway to realize ultra-lo-power mixed-signal NeuSoC, from device arrays and circuits to spike-based deep learning algorithms, with ‘brain-like’ energy-efficiency.

Subject Areas

Cognitive Computing; Deep Learning; Intelligent Cognitive Assistants (ICA); Neuromorphic System-on-a-Chip (NeuSoC); NVRAM; RRAM; Spiking Neural Networks (SNNs).

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