Preprint Article Version 1 This version is not peer-reviewed

A Unified Reconfigurable CORDIC Processor for Floating-Point Arithmetic

Version 1 : Received: 25 June 2018 / Approved: 25 June 2018 / Online: 25 June 2018 (14:42:01 CEST)

How to cite: Fang, L.; Li, B.; Xie, Y.; Chen, H. A Unified Reconfigurable CORDIC Processor for Floating-Point Arithmetic. Preprints 2018, 2018060393 (doi: 10.20944/preprints201806.0393.v1). Fang, L.; Li, B.; Xie, Y.; Chen, H. A Unified Reconfigurable CORDIC Processor for Floating-Point Arithmetic. Preprints 2018, 2018060393 (doi: 10.20944/preprints201806.0393.v1).

Abstract

This paper presents a unified reconfigurable coordinate rotation digital computer (CORDIC) processor for floating-point arithmetic. It can be configured to operate in multi-mode to achieve a variety of operations and replaces multiple single-mode CORDIC processors. A reconfigurable pipeline-parallel mixed architecture is proposed to adapt different operations, which maximizes the sharing of common hardware circuit and achieves the area-delay-efficiency. Compared with previous unified floating-point CORDIC processors, the consumption of hardware resources is greatly reduced. As a proof of concept, we apply it to 1638416384 points target Synthetic Aperture Radar (SAR) imaging system, which is implemented on Xilinx XC7VX690T FPGA platform. The maximum relative error of each phase function between hardware and software computation and the corresponding SAR imaging result can meet the accuracy index requirements.

Subject Areas

reconfigurable architecture; CORDIC; Field Programmable Gate Array(FPGA); SAR imaging

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