Article
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An Ultra-Low-Power Bit-Serial Variable-Accuracy FFT Processor
Yue Lu
*
and Tom Kazmierski
Version 1
: Received: 14 June 2018 / Approved: 14 June 2018 / Online: 14 June 2018 (16:22:15 CEST)
How to cite: Lu, Y.; Kazmierski, T. An Ultra-Low-Power Bit-Serial Variable-Accuracy FFT Processor. Preprints 2018, 2018060240 (doi: 10.20944/preprints201806.0240.v1). Lu, Y.; Kazmierski, T. An Ultra-Low-Power Bit-Serial Variable-Accuracy FFT Processor. Preprints 2018, 2018060240 (doi: 10.20944/preprints201806.0240.v1).
Abstract
In this paper, a new approach is proposed for designing ultra-low-power FFT (Fast Fourier Transform) system suitable for use in energy harvesting powered sensors. Bit-serial architecture is adopted to reduce the power consumption of butterfly operation. Simulation results show that, compared with state-of-the-art bit-serial and conventional parallel processors, the proposed technique is superior in terms of silicon area, power consumption, dynamic energy use due to variable precision arithmetic. A sample design of a 64-point FFT shows that the implementation can save about 40% area and 36% leakage power compared with a conventional parallel counterpart, accordingly achieving significant power benefits at a low sample rate and low voltage domain. The dynamic variation of the arithmetic precision can be achieved through a simple modification of the controller with hardware area overhead of 10% gate count.
Subject Areas
Bit-serial; Low Power; Variable Accuracy Computing; FFT; Energy Harvesting; VLSI; Hardware Design
Copyright: This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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