This study aims to verify the time-variant feature of American ginseng (AG) continuous cropping obstacles and to explore the factors impeding continuous cropping. We verified the feature with a plant-soil feedback pot experiment and then investigated the factors by comparing the properties of control soils that had not been previously used for growing ginseng (CS) with those of soils with a 10-year-crop-rotation cycle following the growth of AG (RS). It’s found that the survival rate of AG in RS was lower than that in CS. The RS had lower pH, available potassium content, and urease activity. Additionally, p-coumaric, p-hydroxybenzoic, vanillic, caffeic, and cinnamic acid levels were lower in RS than in CS, but salicylic acid levels showed the opposite pattern. RS had higher Rhodanobacter and lower Acidothermus, Sphingomonas relative abundances in bacterial community. It’s also found that many bacteria were substantially correlated with phenolic acids and soil physiochemical properties. Results indicate that even after 10-year crop rotation, the negative effects of prior continuous cropping of AG has not been eliminated. The growth of AG can be affected negatively with deterioration of soil physicochemical properties and with lower levels of phenolic acids which promote pathogen reproduction. Probiotics reduction also weighs. Moreover, biotic factors are interrelated with abiotic ones. Therefore, it can be inferred that the comprehensive change of soil properties is the main obstacle for continuous cropping.

When the distance between an obstacle and a power line is less than the discharge distance, a discharge arc can be generated, resulting in interruption of power supplies. Therefore, regular safety inspections are necessary to ensure safe operations of power grids. Tall vegetation and buildings are the key factors threatening the safe operation of extra high voltage transmission lines within a power line corridor. Manual or LiDAR based-inspections are time consuming and expensive. To make safety inspections more efficient and flexible, a low-altitude unmanned aerial vehicle remote-sensing platform equipped with optical digital camera was used to inspect power line corridors. We propose a semi-patch matching algorithm based on epipolar constraints using both correlation coefficient and the shape of its curve to extract three dimensional (3D) point clouds for a power line corridor. Virtual photography was used to transform the power line direction from approximately parallel to the epipolar line to approximately perpendicular to epipolar line to improve power line measurement accuracy. The distance between the power lines and the 3D point cloud is taken as a criterion for locating obstacles within the power line corridor automatically. Experimental results show that our proposed method is a reliable, cost effective and applicable way for practical power line inspection, and can locate obstacles within the power line corridor with measurement accuracies better than ±0.5 m.

Clock Network Design (CDN) is a critical step while designing any Integrated-Circuits (ICs). It holds vital importance in the performance of entire circuit. Due to continuous scaling, 3D ICs stacked with TSV are gaining importance, with an objective to continue with the Moore's law. Through-Silicon-Via (TSV) provides the vertical interconnection between two die, which allows the electrical signal to flow through it. 3D ICs has many advantages over conventional 2D planar ICs like reduced power, area, cost, wire-length etc. The proposed work is mainly focused on power reduction and obstacle avoidance for 3D ICs. Various techniques have already been introduced for minimizing clock power within specified clock constraints of the 3D CND network. Proposed 3D Clock Tree Synthesis (CTS) is a combination of various algorithms with an objective to meet reduction in power as well as avoidance of obstacle or blockages while routing the clock signal from one sink to other sink. These blockages like RAM, ROM, PLL etc. are fixed during the placement process. The work is carried out mainly in three steps- first is Generation of 3D Clock tree avoiding the blockages, then Buffering and Embedding and finally validating the results by SPICE simulation. The experimental result shows that our CTS approach results in significant 9% reduction in power as compare to the existing work.