In this paper, based on the pseudo-totem pole (PTP) circuit, a family of five-level PTP dual boost converters (PDBC) is proposed. Dual boost converter has some unique advantages such as no bridge arm shoot-through risk and no switch body diode reverse recovery problem, so that it has a good application prospect. Compared with conventional three-level PTP converters, PDBCs has higher power density, higher efficiency, and low voltage and current stress. The topological derivation process, working principle, modulation and strategy of the topology are analyzed firstly. Further, the number of power devices, the switches voltage and current stress of the proposed topology is analyzed. Finally, a representative five-level PDBC experimental prototype is designed with AC input 220V/50Hz, DC output 400V/1kW, and peak efficiency of 98.27%. The experimental results show that the five-level PDBC proposed in this paper has higher efficiency and verify the correctness of the topology.

In this paper, a buck DC-DC converter with the proposed twin frequency control scheme (TFCS) and accurate load current sensing (ALCS) have been designed and implemented with 0.18µm CMOS technology for a supply voltage ranging from 2.0-3.0V which is compatible with state-of-the-art batteries (NiCd/NiMH: 1.1-2V, Li-Ion: 2.5-4.2V). The proposed converter yields a peak efficiency of about 92.7% with a load current of 30mA. Furthermore, it only occupies a silicon area of 1.3mm2. The proposed buck converter is dedicated for smartphone applications whereby it spends most of its time in idle, low load conditions.

This study proposes self-calibration of capacitor mismatch errors for high-resolution pipeline analog-to-digital converters (ADCs). The proposed calibration circuit recursively amplifies the capacitor mismatch error by re-utilizing a multiplying digital-to-analog converter in a pipeline stage without increasing the circuit complexity, and the amplified error voltage is converted into digital code by utilizing the remaining pipeline stages. Error correction is performed by subtracting the digital code from the ADC output during normal operation. A prototype of a 12-bit pipeline ADC is fabricated in a 0.18 µm standard CMOS process. The ADC comprises eight 1.5-bit stages, followed by a 4-bit flash ADC as the final stage; the capacitor mismatch errors in the first two pipeline stages are corrected by utilizing the proposed self-calibration technique. At a sampling rate of 30 MS/s, the measured differential and integral nonlinearities improve from +0.82/-0.75 and +1.12/-1.79 to +0.45/-0.41 and +0.47/-0.91 after calibration, respectively. Further, the measured dynamic performances improve significantly with calibration. For an input frequency of 2.09 MHz, the ADC achieves a spurious-free dynamic range (SFDR) and signal-to-noise and distortion ratios (SNDR) of 69.3dB and 63.9dB before calibration, respectively. After calibration, the SFDR and SNDR increase to 84.1dB and 68.9dB, respectively, and the effective number of bits is approximately 11.1bit. The power consumption of the ADC is 35mW under 1.8V supply, and the resulting figure of merit is 514fJ/conversion step.

The medium-voltage DC (MVDC) technology has gained increasing interests in recent years. Power electronics devices dominate those grids. Accurate simulation of such a grid, with detailed models of switching semiconductors, can quickly became very time-consuming, according to the number of connected devices to be simulated. A simulation approach based on interactions on a continuous time model can be very interesting, especially for developing a system level control model of such a modern MVDC distribution grid. Aim of this paper is to present all the steps required for obtaining a continuous time modelling of a +/- 10 kV MVDC grid case study, including Solid State Transformer (SST) and Modular Multilevel Converter (MMC) based Active Front End (AFE). Additional aim of this paper is to supply an educational content about the use of the continuous time simulation approach, thanks to a detailed description of the various devices modelled into the presented MVDC grid. The results of a certain number of simulation scenarios are eventually presented.

This paper presents two control design strategies for voltage regulation in a single inductor dual output (SIDO) DC-DC Buck converter system. Based on a nominal multiple input multiple output (MIMO) plant model and performance requirements, both an LQR and a decoupled PI control laws are designed to control the power converter system, under parametric uncertainties such as voltage source variation, CPL power variation, and load resistance variation. Therefore, the SIDO converter can cascade operating, which may cause the undesired effects of voltage oscillation and reduce the system's stability margin. The control performance was assessed under both uncertainties resistive loading and power variation of a constant power load (CPL). A SIDO DC-DC Buck converter board has been developed for experimental tests. The experimental results show that the LQR strategy, compared to the PI strategy, presented a robust performance in the presence of parametric uncertainties in the resistive loads being, however, sensitive to uncertainties due to the presence of CPL loads.