Article
Version 1
Preserved in Portico This version is not peer-reviewed
A Self-Calibration of Capacitor Mismatch Error for Pipeline ADCs
Version 1
: Received: 8 October 2023 / Approved: 9 October 2023 / Online: 9 October 2023 (11:09:13 CEST)
A peer-reviewed article of this Preprint also exists.
Seo, D.-H.; Cho, S.; Kim, J.-G.; Lee, B.-G. A Self-Calibration of Capacitor Mismatch Error for Pipeline ADCs. Appl. Sci. 2023, 13, 12322. Seo, D.-H.; Cho, S.; Kim, J.-G.; Lee, B.-G. A Self-Calibration of Capacitor Mismatch Error for Pipeline ADCs. Appl. Sci. 2023, 13, 12322.
Abstract
This study proposes self-calibration of capacitor mismatch errors for high-resolution pipeline analog-to-digital converters (ADCs). The proposed calibration circuit recursively amplifies the capacitor mismatch error by re-utilizing a multiplying digital-to-analog converter in a pipeline stage without increasing the circuit complexity, and the amplified error voltage is converted into digital code by utilizing the remaining pipeline stages. Error correction is performed by subtracting the digital code from the ADC output during normal operation. A prototype of a 12-bit pipeline ADC is fabricated in a 0.18 µm standard CMOS process. The ADC comprises eight 1.5-bit stages, followed by a 4-bit flash ADC as the final stage; the capacitor mismatch errors in the first two pipeline stages are corrected by utilizing the proposed self-calibration technique. At a sampling rate of 30 MS/s, the measured differential and integral nonlinearities improve from +0.82/-0.75 and +1.12/-1.79 to +0.45/-0.41 and +0.47/-0.91 after calibration, respectively. Further, the measured dynamic performances improve significantly with calibration. For an input frequency of 2.09 MHz, the ADC achieves a spurious-free dynamic range (SFDR) and signal-to-noise and distortion ratios (SNDR) of 69.3dB and 63.9dB before calibration, respectively. After calibration, the SFDR and SNDR increase to 84.1dB and 68.9dB, respectively, and the effective number of bits is approximately 11.1bit. The power consumption of the ADC is 35mW under 1.8V supply, and the resulting figure of merit is 514fJ/conversion step.
Keywords
capacitor-mismatch calibration; self-calibration; switched-capacitor circuit; pipeline analog-to-digital converter
Subject
Engineering, Electrical and Electronic Engineering
Copyright: This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
Comments (0)
We encourage comments and feedback from a broad range of readers. See criteria for comments and our Diversity statement.
Leave a public commentSend a private comment to the author(s)
* All users must log in before leaving a comment
