ARTICLE | doi:10.20944/preprints202107.0403.v1
Online: 19 July 2021 (10:51:37 CEST)
This paper describes a new optimization methodology of testing vector sets reduction for testing of soft-processor cores and their individual blocks. The deterministic test vectors both for whole core and its individual blocks are investigated that significantly reduce the testing time and amount of test data that needs to be stored on the tester memory. The processor executes an assembler program which together with determined testing vectors ex-ercise its functionality. The new BIST methodology applicable at industrial testing of processor cores, diagnostics and dynamic reconfiguration of FPGA is proposed. This novel methodology combined with dynamic reconfiguration of FPGAs can be profitable applied for missions-critical i.e. FPGAs operate in space, or other difficult condition where are explore on radiation. Experimental results demonstrate that the proposed approach reduces many times testing time.
ARTICLE | doi:10.20944/preprints202101.0550.v1
Subject: Engineering, Automotive Engineering Keywords: edge-computing; processors; hardware acceleration
Online: 27 January 2021 (09:59:46 CET)
Computing in the cloud-edge continuum, as opposed to cloud computing, relies on high performance processing on the extreme edge of the IoT hierarchy. Hardware acceleration is a mandatory solution to achieve the performance requirements, yet it can be tightly tied to particular computation kernels, even within the same application. Vector-oriented hardware acceleration has gained renewed interest to support AI applications like convolutional networks or classification algorithms. We present a comprehensive investigation of the performance and power efficiency achievable by configurable vector acceleration subsystems, obtaining evidence of both the high potential of the proposed microarchitecture and the advantage of hardware customization in total transparency to the software program.
ARTICLE | doi:10.20944/preprints201912.0223.v1
Subject: Engineering, Electrical & Electronic Engineering Keywords: laser dynamics; parallel computing; cellular automatas; GPUs and Multi-Core processors performance
Online: 17 December 2019 (09:48:23 CET)
In this paper we show how to efficiently implement parallel discrete simulations on Multi-Core and GPU architectures through a real example of application: a cellular automata model of laser dynamics. We describe the techniques employed to build and optimize the implementations using OpenMP and CUDA frameworks. We have evaluated the performance on two different hardware platforms that represent different target market segments: high-end platforms for scientific computing, using an Intel Xeon Platinum 8259CL server with48cores and also an NVIDIA Tesla6V100 GPU, both running on Amazon Web Server (AWS) Cloud, and on a consumer-oriented platform, using an Intel Core i9 9900k CPU and an NVIDIA GeForce GTX 1050 TI GPU. Performance results are compared and analysed in detail. We show that excellent performance and scalability can be obtained in both platforms, and we extract some important issues that imply a performance degradation for them. We also found that current Multi-Core CPUs with large core numbers can bring a performance very near to that of GPUs, even similar in some cases.
ARTICLE | doi:10.20944/preprints201805.0242.v2
Subject: Engineering, Electrical & Electronic Engineering Keywords: digital controller; digital signal processors (DSP); modular multilevel converters (MMC), multi-terminal DC network (MTDC)
Online: 14 June 2018 (03:17:20 CEST)
This paper presents the design and implementation of a digital control system for modular multilevel converters (MMC) and its use in a 5-kW small scale prototype. To achieve higher system control reliability and multi-functionality, the proposed architecture has been built with an effective split of the control tasks between a master controller and six slave controllers, one for each of the six arms of the converter. The MMC prototype have been used for testing both converter and system level controls in a reduced scale laboratory set up of a Multi-Terminal DC transmission network (MTDC). The whole control has been tested in order to validate the proposed control strategies. The tests performed at system level allowed to explore the advantages of using an MMC in a MTDC system.