Preprint Article Version 1 Preserved in Portico This version is not peer-reviewed

Optimal Reduction of Number of Test Vectors for Soft Processor Cores Implemented in FPGA

Version 1 : Received: 17 July 2021 / Approved: 19 July 2021 / Online: 19 July 2021 (10:51:37 CEST)

How to cite: Węgrzyn, M.; Jamro, E.; Dąbrowska-Boruch, A.; Wiatr, K. Optimal Reduction of Number of Test Vectors for Soft Processor Cores Implemented in FPGA. Preprints 2021, 2021070403 (doi: 10.20944/preprints202107.0403.v1). Węgrzyn, M.; Jamro, E.; Dąbrowska-Boruch, A.; Wiatr, K. Optimal Reduction of Number of Test Vectors for Soft Processor Cores Implemented in FPGA. Preprints 2021, 2021070403 (doi: 10.20944/preprints202107.0403.v1).

Abstract

This paper describes a new optimization methodology of testing vector sets reduction for testing of soft-processor cores and their individual blocks. The deterministic test vectors both for whole core and its individual blocks are investigated that significantly reduce the testing time and amount of test data that needs to be stored on the tester memory. The processor executes an assembler program which together with determined testing vectors ex-ercise its functionality. The new BIST methodology applicable at industrial testing of processor cores, diagnostics and dynamic reconfiguration of FPGA is proposed. This novel methodology combined with dynamic reconfiguration of FPGAs can be profitable applied for missions-critical i.e. FPGAs operate in space, or other difficult condition where are explore on radiation. Experimental results demonstrate that the proposed approach reduces many times testing time.

Subject Areas

Processors testing; FPGA; test optimization

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