ARTICLE | doi:10.20944/preprints202101.0202.v1
Subject: Engineering, Electrical And Electronic Engineering Keywords: Stochastic Logic; Chaotic Systems; Approximate Computing; Shimizu-Morioka System; Chaotic Circuits; FPGA Implementation
Online: 11 January 2021 (14:56:15 CET)
An exploding demand for processing capabilities related to the emergence of the IoT, AI and big data, has led to the quest for increasingly efficient ways to expeditiously process the rapidly increasing amount of data. These ways include different approaches like improved devices capable of going further in the more Moore path, but also new devices and architectures capable of going beyond Moore and getting more than Moore. Among the solutions being proposed, Stochastic Computing has positioned itself as a very reasonable alternative for low-power, low-area, low-speed, and adjustable precision calculations; four key-points beneficial to edge computing. On the other hand, chaotic circuits and systems appear to be an attractive solution for (low-power, green) secure data transmission in the frame of edge computing and IoT in general. Classical implementations of this class of circuits require intensive and precise calculations. This paper discusses the use of the SC framework for the implementation of nonlinear systems, showing that it can provide results comparable to those of classical integration, with much simpler hardware, paving the way for relevant applications.
ARTICLE | doi:10.20944/preprints202210.0413.v1
Subject: Computer Science And Mathematics, Computational Mathematics Keywords: stochastic logic; chaotic systems; approximate computing; Hindmarsh Rose system
Online: 26 October 2022 (10:33:54 CEST)
In this paper we present a successful implementation of the Hindmarsh–Rose model within a SC environment. The merits of the proposed approach are design simplicity, due to stochastic computing, and the ease of implementation. Simulation results showed that the approximation achieved is equivalent to introducing a noise source into the original model. A study for the level of noise introduced, according to the number of bits in the stochastic sequence, has been performed. Additionally, we demonstrate that such an approach, even though it is noisy, it reproduces the behaviour of biological systems, which are intrinsically noisy. It is also demonstrated that a speedup of x2 compared to biological systems is easily achievable, with a very small number of gates, thus paving the road for the in silico implementation of large neuron networks.
ARTICLE | doi:10.20944/preprints202111.0152.v1
Subject: Engineering, Electrical And Electronic Engineering Keywords: Cellular Nonlinear Networks; Stochastic Logic; real time processing; image processing; memristors.
Online: 8 November 2021 (14:48:16 CET)
Cellular Nonlinear Networks (CNN) are a concept introduced in 1988 by Leon Chua and Lin Yang as a bio-inspired architecture, capable of massively parallel computation. Later on, CNN have been enhanced by incorporating designs that incorporate memristors to profit from their processing and memory capabilities. In addition, Stochastic Computing (SC) can be used to optimize the quantity of required processing elements; thus it provides a lightweight approximate computing framework, quite accurate and effective, though. In this work, we propose utilization of SC in designing and implementing a memristor-based CNN. As a proof of the proposed concept, an example of application is presented. This application combines Matlab and a FPGA in order to create the CNN. The implemented CNN has then been used to perform three different real-time applications on a 512x512 gray-scale and a 768x512 color image: storage of the image, edge detection, and image sharpening. It has to be pointed out that the same CNN has been used for the three different tasks, with the sole change of some programmable parameters. Results show an excellent capability with significant accompanying advantages, like the low number of needed elements further allowing for a low cost FPGA-based system implementation, something confirming the system’s ability for real time operation.
ARTICLE | doi:10.20944/preprints202112.0047.v1
Subject: Engineering, Electrical And Electronic Engineering Keywords: Memristor; memristive grid; maze solving; shortest path; programmable devices.
Online: 3 December 2021 (10:08:55 CET)
In this paper, a system of searching for optimal paths is developed and concreted on a FPGA. It is based on a memristive emulator, used as a delay element, by configuring the test graph as a memristor network. A parallel algorithm is applied to reduce computing time and increase efficiency. The operation of the algorithm in Matlab is checked beforehand and then exported to two different Intel FPGAs: a DE0-Nano board and an Arria 10 GX 220 FPGA. In both cases reliable results are obtained quickly and conveniently, even for the case of a 300x300 nodes maze.
ARTICLE | doi:10.20944/preprints202112.0100.v1
Subject: Engineering, Electrical And Electronic Engineering Keywords: memristor; emulator; analog design; switched capacitor; stochastic computing; mixed signal
Online: 7 December 2021 (11:41:20 CET)
Due to the increased use of memristors, and its many applications, the use of emulators has grown in parallel to avoid some of the difficulties presented by real devices such as variability and reliability. In this paper, we present a memristive emulator designed using a Switched Capacitor (SC), this is, an analog component/ block and a control part or block implemented using stochastic computing (SCo) and therefore fully digital. Our design is thus a mixed signal circuit. Memristor equations are implemented using stochastic computing to generate the control signals necessary to work with the controllable resistor implemented as switched capacitor.