Basic Cells for Reconfigurable Superconducting Kinemonics

1. Introduction

Rapid Single-Flux Quantum (RSFQ) logic, based on the Josephson effect and magnetic flux quantization, has long been a central superconductor digital technology, combining picosecond-scale switching with very low energy dissipation [1,2,3]. As circuit complexity and integration density increase, however, the physical size of both active and passive elements becomes a major scaling constraint. In particular, inductors occupy a substantial fraction of the chip area and limit the functional density of RSFQ circuits [4].

Kinetic inductance offers a direct physical route to reducing this area penalty. In thin or nanostructured superconductors, a substantial part of the inductive energy is stored in the inertia of the superconducting condensate rather than in the magnetic field surrounding the conductor [5,6,7]. Therefore, narrow superconducting segments can provide large inductance per unit length and replace much larger geometric inductors. More broadly, kinetic inductance has become an active design resource in superconducting resonators, detectors, sensors, and quantum-circuit elements, rather than only a parasitic contribution to be minimized [8,9,10].

Beyond enabling circuit miniaturization, kinetic inductance provides additional functionality. Since it depends on the density of superconducting carriers, it can be sensitive to external stimuli and used as a functional, and in some cases tunable, circuit parameter. This principle underlies microwave kinetic inductance detectors, superconducting single-photon detectors, nonlinear kinetic-inductance sensors, tunable microwave resonators, and kinetic-inductance-based quantum elements [11,12,13,14,15,16]. For superconducting computing systems, both classical and quantum, compact kinetic-inductance elements can increase integration density and reduce parasitic magnetic crosstalk by replacing large inductive loops with local nanoscale structures [17].

In this work we use the term “superconducting kinemonics” for circuit architectures in which kinetic inductance acts as a functional control unit (variable) for SFQ-like pulse dynamics. Changing the kinetic inductance modifies the propagation, blocking, splitting, or logical combination of pulses, shifting the design philosophy from fixed superconducting wiring toward compact cells whose assignment or function can be selected after fabrication.

The term “kinemonics” also emphasizes that the proposed logic is based on controlled motion of nonlinear excitations rather than on static voltage levels. In Josephson digital circuits, a logical event is represented by a localized SFQ-like voltage pulse associated with a single magnetic flux quantum:

$$\int V\left(t\right)dt={\Phi }_0,$$

(1)

and by the corresponding transient redistribution of currents in the superconducting branches. In a Josephson transmission line such an excitation is often described as a fluxon or soliton-like pulse. In the lumped all-JJ cells considered here it is not an exact soliton of an integrable continuous model, but it retains the features essential for circuit operation: temporal localization, nonlinear threshold dynamics, and robust transfer from one cell to another [18]. The logic operations studied below can therefore be interpreted as controlled scattering, blocking, splitting, and threshold conversion of soliton-like SFQ events.

The use of kinetic inductors, pioneered as a route to compact superconducting digital circuits, addresses the inductor-area bottleneck but also introduces practical constraints. High-kinetic-inductance elements require tight control of film thickness, material composition or disorder, linewidth, edge quality, interface transparency, and critical-current margins, because all these factors affect the target value and spread of $L_k$. Our approach therefore treats kinetic inductance not as a universal replacement for every inductive element, but as a compact control key used where tunability creates additional functionality. Fixed inductive functions are avoided where possible by relying on all-Josephson-junction cell dynamics, while tunable kinetic-inductance elements are reserved for mode selection and reconfiguration.

A possible physical implementation of such a tunable element is provided by superconducting spin-valve structures, where the relative orientation of ferromagnetic layers modifies the superconducting proximity state and can therefore change the kinetic inductance [19,20]. In circuit terms, this element acts as a kinetic-inductance control key: by switching its inductive state, the same physical cell can be assigned different logical functions. This reconfigurability increases not only the density of individual elements, but also the functional density of the whole superconducting processor, because fewer distinct circuit blocks are needed to implement a larger set of operations. It also provides a mechanism for compensating fabrication spread and adjusting operating points without redesigning the full circuit.

Here we present a set of basic cells for reconfigurable superconducting kinemonics. The library includes a controllable splitter, reconfigurable AND/OR and XOR/OR cells, and a universal programmable logic cell constructed from four reconfigurable gates and one tunable kinetic-inductance element. This universal programmable logic cell implements all sixteen two-input Boolean functions and therefore plays a role analogous to a look-up table, but with the functionality encoded in a configurable hardware basis rather than in a stored truth table.

The paper is organized as follows. Section 2 introduces the normalized Josephson-junction model and the simulation criteria used throughout the work. Section 3 presents the elementary kinetic-inductance-controlled cells: the controllable splitter, the AND/OR gate, and the XOR/OR gate. Section 4 combines these gates into a universal programmable logic cell and discusses its interpretation as a compact reconfigurable Boolean block. Section 5 explains how the same programmable primitives can be interpreted in bio-inspired spiking circuits, where Boolean functions correspond to local operations such as coincidence detection, inhibition, gating, and routing. The influence of tunable kinetic inductance on the soma dynamics of a superconducting spiking neuron is also analyzed there. Section 6 summarizes the implications of the proposed approach for compact reconfigurable digital logic and neuromorphic superconducting hardware.

2. Methodology of Modeling

The nonlinear dynamics of the proposed cells is described by the resistively and capacitively shunted Josephson-junction (RSJC) model [1]. For a conventional Josephson 0-junction, the current–phase relation below the critical current is $I_s=I_{c}sin\phi$, and the total current through the junction is expressed as

$$I=I_{c}sin\phi +{\displaystyle \frac{V}{R_N}}+C{\displaystyle \frac{dV}{dt}},$$

(2)

Here, $R_N$ is the normal resistance, and C is the capacitance of the Josephson junction. After normalisation to the critical current $\widetilde{I_c}$ and the plasma frequency ${\tilde{\omega }}_p=\sqrt{2\pi \widetilde{I_c}/\left({\Phi }_0\tilde{C}\right)}$, the expression takes the following form:

$$i=Asin\left(\phi \right)+\alpha \dot{\phi }+\beta \ddot{\phi }.$$

(3)

Here, dots indicate derivatives with respect to time, t, normalized to the inverse plasma frequency, $\dot{\phi }=2\pi V/\left({\Phi }_0{\tilde{\omega }}_p\right)=V/V_0$, $\alpha ={\Phi }_0{\tilde{\omega }}_p/\left(2\pi \widetilde{I_c}{R}_N\right)$ is a damping coefficient, $A=\pm I_c/\widetilde{I_c}$ is a normalized critical current in case it differs from the normalising current, $\beta =\left(C{\Phi }_0{\tilde{\omega }}_p^2\right)/\left(2\pi \widetilde{I_c}\right)=C/\tilde{C}$.

In all simulations, a logical ’1’ is represented by the arrival of a soliton-like voltage pulse at the corresponding input or output port, whereas logical ’0’ corresponds to the absence of such a pulse within the prescribed time window. A cell is considered to operate correctly if, for each input pattern, the output line produces the pulse sequence required by the target truth table and no additional switching events occur after the transient relaxation time. The inductances are expressed in normalized units,

$$l={\displaystyle \frac{2\pi \widetilde{I_c}L}{{\Phi }_0}},$$

(4)

so that changing of the kinetic inductance modifies the phase-current relation of the corresponding branch and hence the redistribution of current between the Josephson junctions during pulse propagation. The parameter maps shown below were obtained by sweeping the normalized inductances and checking this pulse-level truth-table criterion for all relevant input combinations.

3. Reconfigurable All-Josephson Junction Logic Cells

The elementary cells considered below are designed within the all-Josephson-junction (all-JJ) logic framework, in which SFQ-like pulse propagation and logic operation are governed mainly by Josephson phase dynamics, while large geometric inductors are avoided. Reconfigurability is provided by a tunable kinetic-inductance element, hereafter referred to as a kinetic-inductance control key (KICK) [21]. Changing the effective kinetic inductance of this element modifies the dynamical conditions for pulse transmission through the cell and switches the same circuit topology between two operating modes, for example AND/OR or XOR/OR. Thus, the KICK adds a compact post-fabrication control parameter to an otherwise all-JJ circuit.

In the simulations below, the KICK is treated as a tunable inductive branch with a discrete set of effective values. Microscopically, these values can be associated with different magnetic states of the described multilayer superconducting heterostructure [22,23,24,25,26], such as a spin-valve-type element, in which the proximity-controlled superfluid density changes $L_k$[19,20]. Since $L_k\propto n_s^{-1}$, switching the magnetic state corresponds to switching the effective inductive state. We use this mapping at the circuit level: $L_{\mathrm{on}}$ and $L_{\mathrm{off}}$ define the pass and block regimes of the splitter, whereas other selected values of $L_k$ set the operating mode of the AND/OR and XOR/OR cells. The Josephson-junction topology is kept fixed; only the KICK state changes the dynamical conditions for SFQ-like pulse propagation through the cell.

An important practical advantage of employing tunable kinetic inductance for reconfiguration is the simplicity of control distribution. If the operation mode of a gate were instead selected by its bias current, each gate would require a dedicated current line routed to a specific internal node, which rapidly increases the wiring complexity and on-chip area overhead as the number of gates grows. Our approach simplifies the circuit layout and preserves the compactness of the all-JJ design. Hence, kinetic-inductance-based tuning offers a promising route toward area-efficient and potentially more scalable reconfiguration, as the KICK state is non-volatile and does not require a static bias line.

In the present context, superconducting kinemonics does not simply mean replacing a geometric inductor by a high-kinetic-inductance wire. Instead, it refers to circuit architectures in which kinetic inductance is used as an active design variable controlling the motion, splitting, blocking, delay, or logical combination of soliton-like pulses. For example KICK here is therefore treated as a compact tunable element whose state changes the effective dynamical threshold of a Josephson circuit without requiring a change in the active Josephson-junction layout. This distinction is important: the kinetic inductance is used not only for miniaturization, but also as a post-fabrication and, in principle, dynamically adjustable degree of freedom.

3.1. Splitter

The circuit shown in Figure 1 is a 1-to-4 splitter built from four Kinetic Inductance Controllable Keys (KICKs) connected to a single Josephson junction. In our simulations, we use all-Josephson-junction transmission lines (all-JJTLs), where a single Josephson junction replaces each inductor. The input line and each of the four output branches is implemented as an all-Josephson-junction transmission line (all-JJTL) — a design where every geometric inductor of a conventional JTL is replaced by a single Josephson junction (Figure 1(b)). The standard parameters of each all-JJTL cell are: grounded junctions $J_g$ with $A_g=1$, connecting junctions $J_{con}$ with $A_{con}=0.7$, and bias current $i_b=I_b/{\tilde{I}}_c=0.75$. The KICKs allow the propagation of pulses into each line to be independently enabled or blocked by tuning their kinetic inductance.

The inductance values were selected so that each output line could be controlled independently of the others without affecting the dynamics of the processes occurring within them. Here, $L_{on}$ denotes the inductance value at which pulses pass through to the output line, while $L_{off}$ denotes the value at which pulses are blocked. Figure 2(a) presents a parameter map for possible inductance values. The yellow region indicates pairs ($L_{off}$, $L_{on}$) that ensure correct operation of the splitter scheme, while the blue region corresponds to operational failure. All possible combinations of enabling/disabling the output lines were verified. An increase in the critical current of the connecting Josephson junctions, $J_{con}$, leads to a narrowing of the operational parameter region.

3.2. AND/OR

Utilizing kinetic inductance, it is possible to create a logic cell that operates as AND (for low values of inductance L) or OR (for high values of inductance L) gate. For low inductance values ($L_k<4.68$ in normalized units), the inductor behaves as a weak barrier: a single input pulse cannot supply sufficient current to trigger the output junction $J_{g1}$. Only when two pulses arrive synchronously do their currents add constructively, overcoming the barrier and switching $J_{g1}$; the cell thus operates as an AND gate. At higher inductances ($L_k\in [4.68,5.71]$), the energy storage capability of the kinetic inductor increases considerably. A single pulse now deposits energy in the kinetic inductance (the kinetic energy of the superconducting condensate), and the subsequent release of this stored energy provides an additional current surge that drives $J_{g1}$ well above its critical value. In this regime the cell fires upon receiving any input, behaving as an OR gate. A further increase of $L_k$ beyond the value $5.71$ leads to the formation of several stable states and gives rise to other complex dynamics.

Figure 3. Circuit diagram of a cell with controlled kinetic inductance for switching the circuit’s operation mode between AND and OR logic gates. $J_{con1}$: $A=0.3$. $i_{b1}=1.2$.

Figure 3. Circuit diagram of a cell with controlled kinetic inductance for switching the circuit’s operation mode between AND and OR logic gates. $J_{con1}$: $A=0.3$. $i_{b1}=1.2$.

3.3. XOR/OR

The addition of kinetic inductance enables the cell to function as an XOR gate at $L_k\in [1.32,1.85]$ and as an OR gate at $L>1.85$ (see Figure 4).

In this cell the junction $J_{con2}$ acts as a coincidence-triggered blocking element: a $2\pi$ phase slip of $J_{con2}$ disrupts the propagating soliton-like pulse and prevents it from reaching the output. Because the current driven through this branch scales inversely with the series inductance, $i\sim \Delta \phi /l$, the value of $L_k$ sets the effective threshold for switching $J_{con2}$. For low inductance values ( $L_k\in [1.32,1.85]$ in normalized units), the current delivered to $J_{con2}$ by a single input pulse stays below its critical value, so $J_{con2}$ remains superconducting and the pulse propagates to the output. When two pulses arrive synchronously, the contributions from the two $J_{con1}$ junctions add at the common node, the current through $J_{con2}$ exceeds its critical value, and $J_{con2}$ undergoes a $2\pi$ slip that halts the soliton. The output thus fires for exactly one active input and is suppressed for two coincident inputs, so the cell operates as an XOR gate. For higher inductances ($L_k>1.85$), the series kinetic inductance limits the current reaching $J_{con2}$ below its critical value even for two coincident pulses. The junction $J_{con2}$ can therefore no longer switch, the blocking mechanism is disabled, and every input — single or coincident — propagates to the output. In this regime the cell operates as an OR gate.

We also demonstrate that the functionality of the XOR gate can be further enriched by introducing two additional kinetic inductances into the circuit. The circuit in Figure 5 can be reconfigured to realise the asymmetric function $\overline{A}\wedge B$; specifically, this requires setting $L_{k1}=2.5$ and $L_{k2}=0.5$ (the mirrored function $\overline{B}\wedge A$ is obtained analogously by swapping inductance settings). This transformation is achieved solely by tuning the kinetic inductance values, without any changes to the active Josephson junctions or the addition of new bias lines. The ability to realise the non-commutative function is particularly attractive for neuromorphic or bio-inspired spiking neural networks. In such systems, the directionality of synaptic connections plays a fundamental role: the postsynaptic neuron C may be required to respond to a spike from the neuron B only when the presynaptic neuron A has not fired recently, implementing a form of gated inhibition or a directional receptive field. This operation naturally arises in circuits mimicking spike-timing-dependent plasticity (STDP), where the relative order of pre- and postsynaptic events determines whether a synapse is potentiated or depressed, or in Winner-Take-All architectures, where the activity of one input must selectively suppress or gate another.

4. Reconfigurable Logic Basis and Universal Programmable Cell

Building upon the fundamental AND/OR and XOR/OR gates with controllable kinetic inductance, we propose a novel architecture for a universal programmable logic cell. While the individual reconfigurable gates do not constitute a complete logical basis, the incorporation of a constant logical "1" enables the implementation of inversion functionality through XOR operations, thereby forming a universal set.

The proposed architecture, illustrated in Figure 6, represents an analog of a Look-Up Table (LUT) commonly used in FPGA architectures. However, instead of storing precomputed truth tables in memory, our approach implements a configurable logical basis where the functionality is defined by the operational modes of the kinetic inductance gates. This provides dynamic reconfigurability at the hardware level while maintaining the performance benefits of superconducting electronics.

Through exhaustive computational analysis of all possible gate combinations, we have determined that four reconfigurable gates, supplemented by a tunable kinetic-inductance key on one of the internal signal lines, are sufficient to implement all 16 possible two-input Boolean functions. To identify the minimal gate-level topology capable of realising all sixteen two-input Boolean functions, we performed an exhaustive depth-first search over feed-forward circuits built from reconfigurable AND/OR and XOR/OR gates. The available signal sources are the primary inputs A and B, a constant logical “1”, and the outputs of all previously placed gates. For a fixed total number of gates N, the search recursively constructs a circuit by assigning to each gate:

1.

two input signals chosen from the admissible set, and

2.

a gate type, either AND/OR or XOR/OR.

Once a complete N-gate topology is assembled, its functional coverage is evaluated. For every combination of the gates’ configuration bits (there are $2^N$ possibilities, each selecting the current operating mode of a gate), the output of the circuit is computed for the four input patterns $(A,B)=(0,0),(0,1),(1,0),(1,1)$. The set of distinct truth tables obtained across all configurations forms the coverage mask of the topology. If the mask contains all 16 possible Boolean functions, the circuit is declared universal and the search terminates. If no universal circuit with N gates exists, the search proceeds to $N+1$ gates; since the gate count is increased only after the exhaustive search at the current N fails, the first universal circuit found is guaranteed to use the minimal number of gates.

The optimal configuration comprises two XOR/OR gates and two AND/OR gates arranged in the topology shown in Figure 6, supplemented by a splitter at input A. The splitter distributes the signal into three lines; in one of these lines a tunable kinetic inductance is inserted. This arrangement ensures maximal functional coverage while minimizing the component count and maintaining signal integrity throughout the circuit.

Figure 6. (a) Architecture of the universal programmable logic cell based on reconfigurable all-JJ gates. The circuit consists of four reconfigurable gates (XOR/OR and AND/OR types) and utilizes a constant logical "1" for inversion operations. A splitter at input A distributes the signal, and a tunable kinetic inductance in one of its branches acts as an additional programmable element with two states: pass and block. Together with the four gates, the state of this inductance determines which Boolean function is realised. (b) Circuit-level schematic of the same cell at the Josephson-junction level, showing the individual junctions, bias currents and KICK elements. The parameters of the splitter and of all four gates are listed in Table 1.

Figure 6. (a) Architecture of the universal programmable logic cell based on reconfigurable all-JJ gates. The circuit consists of four reconfigurable gates (XOR/OR and AND/OR types) and utilizes a constant logical "1" for inversion operations. A splitter at input A distributes the signal, and a tunable kinetic inductance in one of its branches acts as an additional programmable element with two states: pass and block. Together with the four gates, the state of this inductance determines which Boolean function is realised. (b) Circuit-level schematic of the same cell at the Josephson-junction level, showing the individual junctions, bias currents and KICK elements. The parameters of the splitter and of all four gates are listed in Table 1.

Table 1. Parameters of the splitter and the four reconfigurable gates of the universal programmable cell (Figure 6). Junction critical currents are given as normalized amplitudes $A=I_c/\widetilde{I_c}$; bias currents are normalized to $\widetilde{I_c}$. A dash denotes an element absent in the given cell.

Cell	Type	${\mathit{A}}_{\mathit{c}\mathit{o}\mathit{n}1}$	${\mathit{A}}_{\mathit{c}\mathit{o}\mathit{n}2}$	${\mathit{A}}_{\mathit{g}1}$	${\mathit{i}}_{\mathit{b}1}$	${\mathit{i}}_{\mathit{b}2}$
Splitter	1-to-3	0.7	0.3	1.0	1.0	0.95
$1g$, $2g$	XOR/OR	0.6	0.75	0.25	0.6	0.25
$2g$, $4g$	AND/OR	0.3	–	1.0	1.2	–

Table 1. Parameters of the splitter and the four reconfigurable gates of the universal programmable cell (Figure 6). Junction critical currents are given as normalized amplitudes $A=I_c/\widetilde{I_c}$; bias currents are normalized to $\widetilde{I_c}$. A dash denotes an element absent in the given cell.

Cell	Type	${\mathit{A}}_{\mathit{c}\mathit{o}\mathit{n}1}$	${\mathit{A}}_{\mathit{c}\mathit{o}\mathit{n}2}$	${\mathit{A}}_{\mathit{g}1}$	${\mathit{i}}_{\mathit{b}1}$	${\mathit{i}}_{\mathit{b}2}$
Splitter	1-to-3	0.7	0.3	1.0	1.0	0.95
$1g$, $2g$	XOR/OR	0.6	0.75	0.25	0.6	0.25
$2g$, $4g$	AND/OR	0.3	–	1.0	1.2	–

The programmable cell is configured by setting the state of five tunable kinetic inductances: one in the splitter (pass or block) and one in each of the four gates, which determines their operational mode (AND/OR or XOR/OR). This configurability enables the same physical circuit to implement diverse logical functions, including but not limited to: AND, OR, XOR, NAND, NOR, XNOR, and various implication functions.

Potential applications of this technology include:

• dynamically reconfigurable superconducting processors for adaptive computing;
• energy-efficient neuromorphic computing systems requiring programmable connectivity;
• quantum-classical interface circuits with adaptable signal processing capabilities.

The universal cell described earlier requires an external constant “1” line to implement inversion within the logic fabric. A more compact and self-contained variant can be obtained by placing a single D-flip-flop with complementary outputs on only one of the primary inputs, for instance on input A. The flip-flop stores the logical value of A and simultaneously provides both the true (A) and inverted ($\overline{A}$) versions of this variable. A constant “1” is then generated internally by feeding A and $\overline{A}$ into additional AND/OR gate configured as an OR gate; as long as the clocked data is held, the output of this OR remains a stable logical “1”. D-flip-flops with complementary outputs are standard primitives in superconducting digital libraries (the RSFQ DRO intrinsically offers both true and inverted outputs), so the modification introduces no fabrication overhead. The topology of the original four-gate universal block remains unchanged; the only difference lies in the way the internal signal pool is created. This arrangement makes the cell autonomous, preserves all sixteen two-input Boolean functions with the same configuration table, and enhances regularity for large-scale reconfigurable systems.

For clarity, we encode each configuration of the universal programmable cell by a five-letter word corresponding to the operating modes of a kinetic inductance and gates 1–4 in Figure 6. For the XOR/OR gates, the letter (X) denotes the XOR mode and (O) denotes the OR mode; for the AND/OR gates, the letter (A) denotes the AND mode and (O) denotes the OR mode; for the tunable kinetic inductance in the splitter line, the letter (P) denotes the pass state (high $L_k$) and (B) denotes the block state (low $L_k$). Thus a configuration word specifies a particular hardware state of the five tunable kinetic-inductance elements. Sweeping all such configuration words produces the full set of sixteen two-input Boolean functions. This representation is useful because it makes the programmable cell closer to a small reconfigurable logic fabric than to a conventional memory-based LUT: the function is selected by physical operating modes of gates rather than by reading a stored truth table.

Table 2. Truth table of all two-input Boolean functions and their relevance to bio-inspired spiking neural networks. Functions are grouped by symmetry and potential use in neuromorphic circuits.

Inputs (A,B)
(0,0)	(0,1)	(1,0)	(1,1)	Function	Configured mode	Neuromorphic relevance
Constant functions
0	0	0	0	FALSE	BAXAX, BAXAO	Complete inhibition (silent)
1	1	1	1	TRUE	BOOAX, BOOAO, BOOOO, POXOO, POOAO, POOOO	Tonic excitation
Symmetric functions
0	0	0	1	AND	PAXAX, PAXAO	Coincidence detection
0	1	1	1	OR	BAOOO, PAXOX, PAXOO, PAOOO	Input integration
0	1	1	0	XOR	BAOOX	Coincidence/ anti-coincidence (STDP)
1	1	1	0	NAND	POOAX	Universal gate
1	0	0	0	NOR	POOOX	Universal gate
1	0	0	1	XNOR	BOXOX	Equivalence detection
Projection and inversion
0	0	1	1	A	BAOAX, BAOAO, PAOAO	Signal pass-through
0	1	0	1	B	BAXOX, BAXOO	Signal pass-through
1	1	0	0	NOT A	BOXAX, BOXAO	Inversion
1	0	1	0	NOT B	BOOOX	Inversion
Asymmetric (inhibition / implication)
0	0	1	0	$A\wedge \neg B$	PAOAX	Directional gating, lateral inhibition
0	1	0	0	$B\wedge \neg A$	PAOOX	Directional gating, lateral inhibition
1	0	1	1	$B\Rightarrow A$	POXOX	Conditional activation
1	1	0	1	$A\Rightarrow B$	BOXOO, POXAX, POXAO	Conditional activation

Table 2. Truth table of all two-input Boolean functions and their relevance to bio-inspired spiking neural networks. Functions are grouped by symmetry and potential use in neuromorphic circuits.

Inputs (A,B)
(0,0)	(0,1)	(1,0)	(1,1)	Function	Configured mode	Neuromorphic relevance
Constant functions
0	0	0	0	FALSE	BAXAX, BAXAO	Complete inhibition (silent)
1	1	1	1	TRUE	BOOAX, BOOAO, BOOOO, POXOO, POOAO, POOOO	Tonic excitation
Symmetric functions
0	0	0	1	AND	PAXAX, PAXAO	Coincidence detection
0	1	1	1	OR	BAOOO, PAXOX, PAXOO, PAOOO	Input integration
0	1	1	0	XOR	BAOOX	Coincidence/ anti-coincidence (STDP)
1	1	1	0	NAND	POOAX	Universal gate
1	0	0	0	NOR	POOOX	Universal gate
1	0	0	1	XNOR	BOXOX	Equivalence detection
Projection and inversion
0	0	1	1	A	BAOAX, BAOAO, PAOAO	Signal pass-through
0	1	0	1	B	BAXOX, BAXOO	Signal pass-through
1	1	0	0	NOT A	BOXAX, BOXAO	Inversion
1	0	1	0	NOT B	BOOOX	Inversion
Asymmetric (inhibition / implication)
0	0	1	0	$A\wedge \neg B$	PAOAX	Directional gating, lateral inhibition
0	1	0	0	$B\wedge \neg A$	PAOOX	Directional gating, lateral inhibition
1	0	1	1	$B\Rightarrow A$	POXOX	Conditional activation
1	1	0	1	$A\Rightarrow B$	BOXOO, POXAX, POXAO	Conditional activation

5. Kinetic Inductances in Spiking Neural Network Elements

Kinetic inductance can also be used in superconducting neuromorphic circuits [27,28,29,30], in particular in bio-inspired spiking neural networks[28,31]. This neuromorphic extension is consistent with the broader view that superconducting electronics can provide ultrafast, low-dissipation hardware for spike-based computation [32], while Josephson junctions naturally support neuron-like threshold, spiking, and bursting dynamics [27,33,34]. In such systems, the main functional elements are the neuron’s soma, the axon-like transmission line, and the synaptic connection. Replacing geometric inductances by tunable kinetic inductances can reduce the occupied area, improve scalability, and suppress parasitic magnetic coupling associated with large inductive loops. At the same time, kinetic inductance provides an additional control parameter for tuning thresholds, propagation delays, and dynamical regimes of spiking elements as demonstrated in Figure 7 and Figure 8.

At the same time the neuromorphic relevance of the universal programmable cell should not be understood as a direct one-to-one mapping between Boolean gates and biological neurons. Instead, the cell provides a compact library of local event-driven operations that are repeatedly needed in spiking neural hardware. In such systems, spikes must be combined, suppressed, delayed, routed, and conditionally transmitted. Boolean functions naturally describe these local operations at the level of pulse presence or absence within a timing window. For example, AND gate implements coincidence detection, OR gate implements input integration, XOR gate implements anti-coincidence or mismatch detection, and asymmetric functions such as $(A\wedge \overline{B})$ implement inhibition or conditional routing.

This interpretation also explains why reconfigurability is especially natural in neuromorphic applications. Unlike conventional fixed digital logic, neuromorphic circuits often require changes of effective connectivity, receptive windows, inhibition patterns, and routing rules. A kinetic-inductance-controlled cell can therefore serve as a local programmable element whose function can be adapted without redesigning the circuit layout. In this sense, the same universal cell bridges conventional Boolean logic and spike-based neuromorphic processing.

5.1. Neuromorphic Applications of the Universal Programmable Cell

As previously noted, the proposed universal cell can be used for a variety of neuromorphic applications. Furthermore, to utilize it in neuromorphic or bio-inspired systems, it is not necessary to implement all 16 Boolean operations, which significantly simplifies the cell’s configuration and fabrication. In this subsection, we have endeavored to provide a fairly comprehensive overview of the potential applications of the universal cell in different ’logical states’ that are related to the functioning of living neural structures and the underlying mechanisms.

For greater convenience, we will categorize the possible applications by logical Boolean functions that the Universal Programmable Cell (UPC) can realize.

• $OR$
  Implementation of simple summation of neural signals at the input of a postsynaptic neuron, where both input signals, even individually, exceed the neuron’s threshold value.
• $NOR$
  This mode could be used to emulate spontaneous activity, suppressed by any input.
• $AND$
  Long-Term Potentiation (LTP). One of the mechanisms of Spike-timing-dependent plasticity (STDP). The idea is as follows: suppose there is a signal $A_0$ that needs to be transmitted between two neurons via a synaptic connection. To implement STDP, we split signal $A_0$ into two identical signals, A and B, which we feed into the input of a universal block. The signal B is applied with a delay of $\tau$. Consequently, the output of the block will produce a signal corresponding to the intersection ($A\wedge B$) of two copies of the same signal, offset by the amount of $\tau$.
  Spatial/Temporal summation (Threshold activation). The UPC only transmits a signal when signals A and B are received synchronously at its input.
  Coincidence Detection. The operating principle is similar to that of LTP, but the UPC receives two different signals: if both arrive simultaneously, the UPC generates an output signal, otherwise, it generates nothing.
  Associative learning. Similar to a coincidence detector, but used for Hebbian learning mechanism.
• $XOR$
  Conscious control of reflex actions, where decisions are made automatically at the spinal cord level but can be further controlled at the brain level. For example, the act of holding a cup of hot tea in your hands. On the one side, the body tries to let go of the cup to relieve the pain, but the brain realizes that if it does so, the cup will break and the tea will spill, so it forces the body to hold the hot cup (signals 1 and 1). At the same time, if there is no cup, then there is nothing to decide (0,0). If the brain does not interfere with the spinal cord’s function, the hand will naturally relax and the cup will fall (1,0). Similarly, even if the cup is cold, the brain may send a signal to relax the fingers, leading to the expected result (0,1).
• $A\wedge \overline{B}$ (inhibition, i.e. the negation of the implication $A\Rightarrow B$)
  Long-Term Depression (LTD) or the saturation effect. The second STDP mechanism, which plays a crucial role in signal transmission between neurons, alongside LTP. The UPC input receives two signals: A and B, with B delayed by a time $\tau$. Since the UPC is configured to implement the inhibition function $A\wedge \overline{B}$, a signal with a duration of $\tau$ will be generated at the block’s output. In other words, signal B is the cut-off of signal A.
  Temporal Filtering/Receptive Windows. Conceptually, this is the same implementation as for the LTD case. Here, delay control is added: a short time window results in high signal selectivity, while a long window leads to integration. This is another mechanism, alongside STDP, that allows for the tuning of a neuron’s temporal memory.
  Inhibiting activity. Being in decrement mode, the UPC can mimic the behavior of a single inhibitory neuron. If we assume that input A corresponds to the signal from an excitatory neuron and input B corresponds to the signal from a conditionally inhibitory neuron, then when the two signals are synchronized, the system’s output will always be zero. If there is no signal at input B, signal A will pass through the block.
  Winner-Take-All. Suppose we have several UPC whose inputs $A_n$ are responsible for transmitting excitatory signals, and whose inputs $B_n$ are responsible for inhibitory signals. Then, if we feed the output signal of each UPC to the inhibitory input of all other blocks, we obtain a Winner-Take-All mode: the block that received the excitatory signal first wins (its signal can proceed further). Such a circuit paves the way for modeling competition processes, lateral inhibition, and selectivity.
  Realization of the refractory period. The UPC output signal is supplied to its inhibiting input B via a feedback delay circuit. Thus, the signal received at input A temporarily prevents the block from being reactivated.
  Oscillatory Dynamics / Rhythmogenesis / Synchronization. By connecting several blocks via delay lines and adding excitation and inhibition signals (A and B), it is possible to emulate steady-state oscillations, burst dynamics, and phase locking, which paves the way for modeling brain rhythms.
• $AND$ with ($A\wedge \overline{B}$)
  Full STDP mechanism realization (LTP and LTD). The combination of the LTP and LTD mechanisms described above, where the output of the LTP circuit serves as the input signal $A_2$ for LTD. The signal B from the LTP circuit, delayed by a time constant ${\tau }_2$, is used as the signal $B_2$ for LTD. Using this type of circuit prevents signal A from passing indefinitely and emulates the effect of a decrease in neurotransmitter concentration in the synaptic gap (the fatigue effect).
  Spike-Timing Routing. Implementation of a system for controlling the arrival delay of spikes in complex circuits using STDP mechanisms.

5.2. Kinetic Inductance in the Neuron Soma

The neuron soma is the part of a spiking element where the input stimulus is integrated and converted into an output voltage spike. Earlier, we proposed a superconducting bio-inspired neuron intended for operation in spiking neuromorphic networks [35] that emulate basic patterns of biological neural activity. In that design, the dynamical regime of the neuron is controlled by the circuit parameters and by the external bias current $i_b$. Since the generation of an output voltage spike is determined by the phase dynamics of the Josephson circuit, replacing selected geometric inductances by kinetic inductances offers a direct way to tune the soma dynamics after fabrication.

Taking the parameters of the regular mode of a spiking bio-inspired neuron from [31] as a basis and replacing the geometric inductances l, $l_S$ and $l_{SQ}$ ($=l+l_S$) in the neuron’s soma with kinetic ones we have observed how the neuron’s operating regimes changed during kinetic inductance variation. The reference point was based on the following parameter values: $I_b/I_{C3}=2.5$, Josephson damping parameters ${\alpha }_{1,2,3}=0.78$ (in [31] they were designated by ${\Gamma }_{1,2,3}$), $I_{C1}/I_{C3}=1$ and $I_{C2}/I_{C3}=0.97$. Note that a sequence of rectangular pulses at the input with a total level $A_{in}=0.5$, period $T_{in}=120·t_p$ and duration of one pulse ${\tau }_{in}=20·t_p$ was used as an external stimulus (here $t_p$ is the inverse plasma frequency, defined in the Section 2). Varying the indicated kinetic inductances with the other parameters fixed revealed three basic modes of neuron operation: regular mode (RM), steady state mode (SSM) and bursting mode (BM). In Figure 8 all the mentioned modes are marked with the corresponding designations. A separate area is occupied by the so-called non-biological mode of operation (NBM), which is characterised by continuous generation of spikes without any external influence (no input stimulus signal) and pattern activity. Typical spike-generation patterns of the neuron in all four regimes are shown in Figure 9.

6. Discussion and Conclusions

We have presented a compact set of basic cells for reconfigurable superconducting kinemonics, where kinetic inductance is used not only as a replacement for bulky geometric inductors but also as a functional control parameter. The proposed cells include a controllable splitter and two reconfigurable logic gates, AND/OR and XOR/OR. In each case, changing the kinetic inductance modifies the propagation of SFQ-like pulses and selects the operating mode of the same physical circuit.

Combining these elementary cells, we constructed a universal programmable logic cell consisting of four reconfigurable gates and a single tunable kinetic-inductance key. The cell can implement all sixteen two-input Boolean functions and therefore provides a superconducting analogue of a look-up table. In contrast to a conventional LUT, however, the functionality is not stored as a truth table in memory; it is defined by the selected modes of the kinetic-inductance-controlled gates. This makes the proposed architecture attractive for dense superconducting circuits where functional density, compactness, and post-fabrication tunability are equally important.

We also considered the role of kinetic inductance in superconducting spiking-neuron elements. In the neuron soma, replacing selected geometric inductances by kinetic inductances allows one to tune the dynamical regime of the circuit and to shift the boundaries between regular spiking, steady-state, bursting, and self-oscillatory operation. Thus, the same design principle can be used both in reconfigurable digital logic and in bio-inspired superconducting neuromorphic circuits.

The main practical advantage of this approach is the simultaneous reduction of footprint and parasitic magnetic coupling. Smaller inductive loops reduce unwanted flux cross-talk, while tunable kinetic inductance provides an additional degree of freedom for compensating fabrication spread and adjusting the circuit after fabrication. The present results are based on numerical modelling; the experimental outlook is summarized at the end of this section.

The relevant scaling metric is therefore not only the physical area of an individual inductor, but also the functional density of the circuit, i.e., the number of distinct operations that can be implemented per unit area and per active circuit element. A fixed superconducting logic library increases functional density mainly by shrinking individual cells. A reconfigurable library adds a second mechanism: the same physical cell can be assigned different logical roles in different parts of a circuit or at different stages of operation. In this sense, kinetic-inductance tuning provides a hardware-level analogue of programmability, while preserving the picosecond-scale pulse dynamics and low dissipation characteristic of Josephson logic.

The proposed architecture also clarifies the relation between conventional digital superconducting logic and neuromorphic superconducting circuits. In the digital interpretation, the universal programmable cell is a compact reconfigurable Boolean primitive: it implements all sixteen two-input functions and can therefore be used as a hardware analogue of a small LUT. In the neuromorphic interpretation, the same set of functions describes local spike-processing motifs: coincidence detection, inhibition, conditional transmission, routing, refractory blocking, and winner-take-all competition. Thus the digital and neuromorphic uses are not separate applications of unrelated devices; they are two interpretations of the same kinetic-inductance-controlled pulse logic.

This point is important because reconfigurability has a different status in the two cases. For conventional digital logic, reconfigurability is a route to higher functional density, post-fabrication correction of parameter spread, and reduced need for specialized cells. For neuromorphic hardware, reconfigurability is even more fundamental: adaptation, plasticity, and task-dependent connectivity are intrinsic parts of the computational model. A fixed superconducting spiking network would be limited to one hard-wired architecture, whereas a network built from reconfigurable kinemonic cells can modify local gating rules and effective inter-neuron connections directly on chip.

Therefore, tunable kinetic inductance provides more than a compact replacement for geometric inductors. It supplies a physically natural control variable for superconducting hardware in which compactness, low dissipation, and programmability must coexist. The next essential step is an experimental demonstration of the proposed KICK-based cells, including measurements of switching margins, timing jitter, parameter tolerance, reprogramming stability, and multi-cell operation. Such experiments will determine the practical operating window of superconducting kinemonics and its prospects as a common hardware platform for dense reconfigurable logic and cryogenic spiking neural networks.