On Recent Advances in Design of Transimpedance Amplifiers in CMOS: A Taxonomy of Topological Enhancements Beyond the Transimpedance Limit

Transimpedance amplifiers (TIAs) are the critical current-to-voltage interface in optical receivers, LiDAR front-ends, biomedical sensors, and unconventional applications such as magnetic-resonance receiver-coil arrays and wide-bandgap ultraviolet detectors, and their CMOS design is governed by a fundamental gain-bandwidth-noise trade-off whose structure is rarely made explicit. This review introduces a unifying framework rooted in three explicit assumptions underlying the classical shunt-feedback TIA limit: a single-pole core amplifier (A1), a resistive feedback element (A2), and the full input capacitance loading the feedback summing node (A3). Relaxing one or more of these is shown to be the common structural thread behind every class of bandwidth or noise enhancement in the recent literature, and all surveyed architectures are organized into a six-tier taxonomy, from Tier 0 designs operating within the classical limit to Tier 5 topologies that bypass all three assumptions simultaneously. This taxonomy is supplemented by an orthogonal configurability axis spanning single- and dual-control reconfigurable, variable-gain, and dynamic-range-extension designs. We further show that stability is not removed by these relaxations but migrates with the tier, from the global phase margin of the classical loop to a local regulating loop, a group-delay-flatness constraint, an input-passivity condition, or a multi-loop interaction, so that each architecture carries a predictable stability locus alongside its noise and bandwidth consequences. The taxonomy is cross-referenced with application domains, with closed-form noise-floor boundary plots parametrized by input capacitance and amplifier gain-bandwidth product, and with the CMOS technology landscape, where we argue that the most advanced node is not universally optimal and that node and topology act as complementary rather than competing levers. A single consistent figure of merit, applied uniformly to a representative set of CMOS realizations from 0.6 μm to 16 nm FinFET, shows no monotonic improvement with publication year or node and is presented as a diagnostic indicator rather than an absolute ranking. The review closes with an outlook on 200 Gb/s /lane links, wide-bandgap sensor integration, and the FinFET-to-gate-all-around device transition.