A Family of Gallium Arsenide Operational Amplifiers With a Single High-Impedance Node

1. Introduction

Operational amplifiers (Op-Amps) remain key components in a wide range of modern analog and analog-to-digital computing systems today. However, for operation at elevated temperatures, special circuitry of the Op-Amp and circuits for establishing their static mode is required.

In recent years, there has been a growing interest in creating an Op-Amp based on gallium arsenide (GaAs), which is associated with the limitations of silicon technology when operating at high frequencies and under conditions of extreme external influences (radiation, elevated temperatures) [1,2,3].

One of the promising areas in the design of GaAs Op-Amp are circuit solutions with a single high-impedance node, providing average levels of voltage gain [4,5,6].

The relevance and novelty of the article lies in the development of recommendations for the design of original circuit solutions for Op-Amp with one high-impedance node based on gallium arsenide nJFET field-effect and GaAs p-n-p bipolar transistors, which are implemented within the framework of technologies mastered by a number of microelectronic companies [7,8,9,10,11,12,13,14,15,16]. The proposed circuit engineering methods can be used to create analog microcircuits designed to operate at elevated temperatures.

2. The Main Recommendations for Building a GaAs Op-Amp Based on an "Folded" Cascode

The structure of the operational amplifier considered below (Figure 1) is one of the most popular and is used in many serial microcircuits of leading microelectronic companies (154UD3, HA2520, HA5190, OP90, AD797, AD8631, AD8632, AD817, HA-2500, 140UD30, OPA42, etc.). Its feature is the presence of one high–impedance node Σ₁, which allows you to get the average values of the voltage gain.

The total systematic component of the zero offset voltage of the Op-Amp in Figure 1 has three components

:$V_{OS.}=V_{OS.1}+V_{OS.2}+V_{OS.3},$ (1)

where $V_{OS.1}$is determined by the difference between the reference current sources I₁, I₂, and I₃ from the values shown in Figure 1;

$V_{OS.2}$ depends on the non-identity of the gate-drain static voltages of the input transistors M1 and M2;

$V_{OS.3}$ is determined by the current error in the high-impedance node.

The${\mathit{V}}_{\mathit{O}\mathit{S}.1}$score. To obtain small $V_{OS.1}$it is necessary to ensure strict compliance with the requirements for reference current sources I₁, I₂, I₃. Their significant difference from the set values generates the first component of the zero offset voltage ($V_{OS.1}$). In practice, I1, I2 and I3 are implemented on nJFET GaAs field effect transistors.

The${\mathit{V}}_{\mathit{O}\mathit{S}.2}$score. If there is a difference in ΔV_AB, then this generates a second component:

$V_{OS.2}={∆V}_{AB}\mu ,$where μ=10^-2-10^-3 is the internal feedback coefficient of the transistors M1, M2 of the input differential stage in a circuit with a common gate.

If it is not possible to ensure equality V_A = V_B, then a cascoded input cascade must be used as the input differential stage (Figure 2).

The${\mathit{V}}_{\mathit{O}\mathit{S}.3}$score. The third component of $V_{OS.3}$is related to the difference in static currents ${∆I}_1$in the high - impedance node Σ₁ when it is short - circuited to an equipotential voltage source:

$V_{OS.3}={∆I}_1{S}_{DS},$where $S_{DS}$ is the steepness of the gain of the differential stage DS1 from the inputs of the In.1, In.2 in a high-impedance node Σ1.

To reduce V_OS.3 in the diagram in Figure 1, in the high-impedance node Σ1, it is necessary to ensure mutual compensation of all incoming and outgoing currents. For this purpose, it is sometimes possible to use a buffer amplifier control unit, the input current of which should be equal to I_bn, or use special circuits for generating compensating current on bipolar transistors.

Figure 3 shows a variant of the GaAs Op-Amp construction in Figure 1, which ensures the identity of the gate-drain static voltages of the M1, M2 transistors. For this purpose, an auxiliary transistor Q3 and an additional reference current source I₄ are used.

In the Op-Amp circuit in Figure 4, two tasks are solved simultaneously - reducing $V_{OS.2}$ due to the non-identical voltages V_A and V_B, as well as mutual compensation of incoming and outgoing currents in the high-impedance node Σ1, affecting $V_{OS.3}$.

The considered features of the basic Op-Amp in Figure 1 based on the "folded" cascade can be used in the construction of many other variants of GaAs control systems of this class.

In operational amplifiers, there are also other components of the zero offset voltage (except $V_{OS.1}$, $V_{OS.2}$, $V_{OS.3}$ (1)), which are weakly dependent on the circuit solutions used and are determined by process errors, transistor topology, their design and technological features, the presence of a temperature gradient between the transistors of the input differential pair, etc. Currently, effective methods have been developed to reduce these "non-circuit" effects, the essence of which is considered in [17,18,19].

3. The First Practical Circuit of a GaAs Op-Amp is Shown in Figure 5

In this circuit design (Figure 5), the Q9 and VD1 elements ensure the symmetry of static modes in terms of gate-drain voltage of the transistors of the input differential cascade M1, M2.

At the same time, the base current of the Q9 transistor makes it possible to obtain the emitter current of the Q10 transistor equal to I₀+I_bn. As a result, the collector current Q10 is equal to I₀, which corresponds to the drain current of the transistor M11, which is determined by the resistance R7. In this scheme, JFET cascade activation is recommended as M3, M4, and M11.

4. The Second Practical Scheme of GaAs op-amp is Shown in Figure 6

In the Op-Amp circuit in Figure 6, which implements the previously considered circuit techniques for reducing V_OS.Σ (1), all reference current sources are made on JFET transistors, and the resistances of the current-limiting resistors are the same R1=R2=R4=R5=R6, which increases the identity of the reference currents and reduces the component V_OS.1 (1).

Here, using Q7 and Q9 transistors, the identity of the gate-drain static voltages of the input transistors M1, M2 is ensured. In addition, the base current of the Q9 transistor is "added" to the emitter circuit of the Q8 transistor. As a result, when the input current of the buffer amplifier is zero, mutual compensation of incoming and outgoing currents is provided in the high-impedance node Σ₁:

I_c.8=I_d.12=I₀.

5. The Third Practical Scheme of GaAs Op-Amp is Shown in Figure 7

The symmetry of the static modes of the input transistors M1, M2 in the diagram in Figure 7 is provided by the introduction of a two-pole bias circuit V₀, which can be implemented on p-n junctions, resistors or emitter repeaters.

The compensation of the incoming and outgoing currents in the high - impedance node Σ₁ is provided by transistors Q8 and M11:

I_c.7= I₀-I_bn=I_d.11.

6. The Fourth Practical Scheme of GaAs op-amp is Shown in Figure 8

The M9 and M10 transistors in this circuit make it possible to obtain identical gate-drain voltages for M1, M2 transistors, which reduces V_OS.2 (1).

At the same time, the Q12 and M11 transistors provide zero difference current in the high-impedance node Σ₁, which reduces V_OS.3 (1).

7. The Fifth Practical Scheme of GaAs Op-Amp is Shown in Figure 9

In this circuit, elements Q9 and Q10 minimize the second component of the zero offset voltage V_OS.2 (1).

The base current of the Q12 transistor in the diagram in Figure 9 is "added" to the high-impedance node Σ₁, which compensates for the current error. The Q13 transistor symmetrizes the static collector-base modes of Q9 and Q10 transistors. This increases the identity of the currents I₀ generated by the M5-M8 transistors and reduces V_OS.1 (1).

8. The Sixth Practical Scheme of GaAs Op-Amp is Shown in Figure 10

The symmetry of the static modes of the input transistors M1, M2 in the circuit in Figure 10 is provided by the p-n junctions VD1.

To obtain a zero difference current in the high-impedance node Σ₁, an emitter repeater on a Q8 transistor is used, which adds the base current I_bn to node Σ₁. As a consequence:

I_c.7 = I₀ - I_bn + I_b8 = I₀.

9. The Seventh Practical Scheme of GaAs is Shown in Figure 11

This circuit design uses nJFET cascoding in the input stage and reference current sources on M3 and M4 transistors.

The gate-drain voltage balancing circuit M1*, M2* in the form of a two-pole V₀ may not be present in this circuit, since a cascade switch is used in the input stage. This reduces the systematic component of V_OS.2 (1). The Q6 transistor measures the base current of the Q7 transistor (I_bn) and "adds" its value to the source of the M5 transistor. As a consequence, V_OS.3 (1) decreases because

I_c.7 = I₀ - I_bn = I_d.5^*.

10. The Eighth Practical Scheme of GaAs Op-Amp is Shown in Figure 12

A special feature of this circuit design is the use of the JFET cascade switch in the input DS1 and in the reference current sources on the M6, M8, M14 transistors.

At the same time, the reduction of the current error and V_OS.3 (1) is provided by the Q9 transistor, which "adds" the base current I_bn to the high-impedance node Σ₁:

I₀-I_bn+I_b9 =I_d13.

11. The Ninth Practical Scheme of GaAs Op-Amp is Shown in Figure 13

This circuit uses a JFET cascade in the input stage, as well as reference current sources on transistors M5, M8, and M13, M14.

The base current of the Q10 transistor is "added" to the high-impedance node Σ₁, which allows for mutual compensation of incoming and outgoing currents in this node and reduces the third systematic component of the zero offset voltage V_OS.3 (1).

12. The Tenth Practical Scheme of GaAs Op-Amp is Shown in Figure 14

A special feature of the circuit in Figure 14 is the use of the JFET cascade switch in the circuits of the reference current sources I₀, which increases their identity.

The collector current of the transistor Q7 here is I_c7 =I₀-I_bn.

To reduce the difference current in the high-impedance node Σ₁, an emitter repeater on a Q12 transistor is introduced into the circuit, to the output of which a buffer amplifier (BA) is connected.

The identity of the static gate-drain voltages of the transistors of the input stage M1, M2 is provided by the p-n junction VD1.

13. The Eleventh Practical Scheme of GaAs Op-Amp Figure 15

To reduce the second component of the zero offset voltage (V_OS.2) a matching two-pole V₀ is introduced into the circuit in Figure 15, which can be made on p-n junctions, resistors or emitter repeaters.

To reduce the third component of the zero offset voltage, V_OS.3 (1) in the diagram in Figure 15 using the Q8 transistor, the base current of the Q7 transistor is measured, which is then transmitted to the source circuit of the M11 transistor. As a result, when the input current of the control unit is zero, the collector current of the Q7 transistor and the drain current of the M11 transistor are mutually compensated in the high-impedance node Σ₁.

14. The Twelfth Practical Scheme of GaAs Op-Amp is Shown in Figure 16

The peculiarity of this Op-Amp circuit is that the compensation of the current error in the high-impedance node Σ₁ is provided here by transistors Q5 and M4. This reduces V_OS.3 (1).

Due to the use of a JFET cascade switch in the input stage, as well as the use of a cascade-type current mirror, the asymmetry of static modes of DC transistors is minimized in this circuit design, which reduces V_OS.2 (1).

15. An Example of a GaAs Op-Amp Computer Simulation Based on an "Folded" Cascade

Figure 17 shows a GaAs circuit of an operational amplifier with one high-impedance node Σ₁, which uses an input stage on transistors M1 and M2. The current source on the M3 and M4 transistors provides stable current to the common DC source circuit and improves the common-mode signal suppression parameters.

The intermediate stage of the Op-Amp in Figure 17 includes transistors M5, M6, M7, M8 and Q9 with corresponding current-limiting resistors R3, R4, R5 and R6 and contains transistors Q10, M11.

The C_C capacitor performs the function of a frequency correction circuit to ensure circuit stability.

The static mode of the op-amp circuit in Figure 17 in the LTspice environment at R1÷R6 = 20 kOhm, R7 = 20.5 kOhm, Ck = 3 pF, Vc = 5 V, Vs = ±10V is shown in Figure 18.

Figure18. Static mode of transistors Op-Amp in Figure 17.

An analysis of the static mode of the Op-Amp in Figure 18 shows that the transistors of the proposed circuit operate at low currents, which ensures its energy efficiency.

Figure 19 shows the logarithmic amplitude-frequency response (AFR) of the voltage gain coefficient.

The frequency response analysis in Figure 19 shows that the proposed GaAs Op-Amp circuit solution (Figure 17) allows obtaining a high voltage gain in the low frequency range (about 80 dB) and an upper limit frequency of about 5 kHz.

16. Conclusion

Recommendations have been developed for the design of a family of high-temperature gallium arsenide operational amplifiers based on an "folded" cascode with one high-impedance node, the circuits of which are based on GaAs nJFET and GaAs p-n-p bipolar transistors. It is shown that due to the rational construction of static mode control circuits, the Op-Amps under consideration can have relatively small values of the systematic component of the zero offset voltage. The proposed Op-Amp circuits are recommended for practical use in analog devices operating at elevated temperatures (up to 250 °C), which is ensured by the use of GaAs transistors.

The research has been carried out at the expense of the Grant of the Russian Science Foundation (project No. 23-79-10069), https://rscf.ru/en/project/23-79-10069/.