An Enhanced Dynamic Bias Comparator with a Reference-Compensated Offset Calibration Technique

In 180 nm CMOS process, an enhanced dynamic bias comparator with reference-compensated offset calibration technique is implemented. In order to reduce the delay time of the comparator, an enhanced structure is used. To reduce the power consumption, a dynamic bias technique is applied to the comparator. A novel reference-compensated offset calibration technique is introduced to achieve offset calibration. Simulation results indicate that the proposed comparator achieves a delay time of 190.3 ps and an energy consumption of 324.2 fJ/comparison under operating conditions of 150 MHz and an input differential amplitude of 0.1 V. Furthermore, the application of a reference-compensated offset calibration technique facilitated a reduction in the offset voltage of the comparator from 18.1 mV to 6.3 mV.