An Enhanced Dynamic Bias Comparator with a Reference-Compensated Offset Calibration Technique

1. Introduction

Analog-to-digital converters (ADCs) are essential in most systems because electronic devices handle digital data, whereas real-world signals are analog. These converters are now widely used in high-speed high-precision analog front-end circuits for integrated circuit testing, medical imaging, and instrumentation [1,2,3]. In ADCs, comparators are an essential component. Their main function is to quantize the input signal by comparing it to a reference signal, which produces a digital output level [4]. They determine the precision, speed, area, and noise characteristics of the entire ADC [5,6]. As a result, the performance of comparators is crucial to ADC.

Static and dynamic comparators are the two main types. Static comparators have very high power consumption since they are constantly operating. Their speed is also severely constrained in the absence of positive feedback [7]. Dynamic comparators overcome the issue of slow speed through clock-controlled positive feedback, which exhibit no static power consumption [8,9]. Conventional single-stage dynamic comparators require a high voltage margin because they directly stack the input transistor with a cross-coupled differential latch [10]. Single-stage dynamic comparators have advantages in static power consumption, but high-speed circuits cannot be satisfied by their sluggish speed. The two-stage dynamic comparator consists of two sections [11,12,13,14]: the first stage is a pre-amplifier, which amplifies the input signal to increase the sensitivity of the comparator while isolating kickback noise generated by the second stage. The dynamic latch in the second stage amplifies the difference between the output signals of the pre-amplifier and uses positive feedback to determine which input signal is greater. However, the low gain of the first-stage pre-amplifier restricts its capacity to efficiently amplify the input signal. This limitation also leads to inadequate noise suppression performance, which has a detrimental effect on the speed and accuracy of the comparator [15]. Therefore, developing a technique to enhance the speed of comparators is crucial.

Another important performance metric is comparator mismatch, which is typical characterized by offset voltage. Significant physical and electrical mismatches can still occur even with the most symmetrical arrangement and the minimal distances between transistors in layout [17]. Static mismatch and dynamic mismatch are two types of mismatch. The performance of the comparator is deteriorated by both kinds of mismatch since they produce an arbitrary offset voltage [18,19].

Simply increasing transistor size is not an optimal solution because this improvement is limited and also raises power consumption and parasitic capacitance. Offset calibration for a comparator can be accomplished in either the digital or analog domain. Digital calibration can be achieved through digital signal processing circuits or dedicated digital logic, whereas most analog calibration methods require the use of a digital-to-analog converter (DAC). The basic idea behind existing calibration schemes is to introduce a controlled imbalance to compensate for comparator mismatch. These methods include current compensation [9], load compensation [20,21], and threshold compensation [22]. In addition to the hardware overhead of the digital circuitry, these techniques require additional analog circuits to assist in the process of the offset calibration. This inevitably increases the design complexity, area, and power consumption of the analog system.

This paper proposes an enhanced structure to increase the speed of the comparator. A dynamic bias technique is applied to reduces power consumption. Moreover, a reference-compensated offset calibration is suggested to improve the mismatch performance of the comparator. The remainder of this paper is organized as follows. The structure of the proposed comparator is introduced in Section 2. The reference-compensated offset calibration technique is described in Section 3. The simulation results are shown in Section 4. Finally, a discussion is provided in Section 5.

2. Analysis and Design of Comparator

2.1. Analysis of Conventional Comparator

A conventional singe-stage comparator circuit is shown in Figure 1 [16]. The entire circuit consists of two parts: a dynamic comparator and a clock-gated latch. The comparator makes a decision based on the input signal and generates an output using positive feedback. The clock gated latch stores the output data and enhances the output drive capability.

When clock CK is high, the circuit is in the reset state. MP3 is off, and MN3 and MN4 are turned on, nodes X and Y are discharged to $V_{\mathrm{SS}}$. In the clock-gated latch, $v_{\mathrm{OP}}$ and $v_{\mathrm{ON}}$ are reset to $V_{\mathrm{SS}}$.

When clock CK goes low, the comparator begins to work. MP3 is turned on, and MN3 and MN4 are turned off. MN1 and MN2 charge the parasitic capacitances $C_{\mathrm{X}}$ and $C_{\mathrm{Y}}$ at nodes X and Y. The voltages at node X and Y begin to increase.The time taken for voltages $v_{\mathrm{X}}$ and $v_{\mathrm{Y}}$ to rise from $V_{\mathrm{SS}}$ to the threshold voltage $V_{\mathrm{THN}}$ is called the charge time $t_1$, which can be expressed as

$$t_1={\displaystyle \frac{V_{\mathrm{THN}}{C}_{\mathrm{p}}}{I_{\mathrm{CM}}}},$$

(1)

where $C_{\mathrm{p}}$ equals the parasitic capacitances $C_{\mathrm{X}}$ and $C_{\mathrm{Y}}$ of nodes X and Y. $I_{\mathrm{CM}}$ is the common-mode current. From formula (1), it can be seen that the charge time is related to the parasitic capacitance at its output node; the smaller the parasitic capacitance, the smaller the charge time. Additionally, the charge time is correlated with the common-mode current; the higher the common-mode current, the smaller the charge time. It is evident that an voltage difference between $v_{\mathrm{IN}}$ and $v_{\mathrm{IP}}$ results in amplified disparities in the charge currents of MP1 and MP2, leading to an enhancement in the voltage difference between $v_{\mathrm{X}}$ and $v_{\mathrm{Y}}$, which can be written as

$$v_{\mathrm{XY}0}=g_{\mathrm{mp}}(v_{\mathrm{IP}}-v_{\mathrm{IN}})t_1={\displaystyle \frac{V_{\mathrm{THN}}{C}_{\mathrm{p}}}{I_{\mathrm{CM}}}}{g}_{\mathrm{mp}}(v_{\mathrm{IP}}-v_{\mathrm{IN}}),$$

(2)

where $g_{\mathrm{mp}}$ equals the small-signal transconductance $g_{\mathrm{mp}1}$ and $g_{\mathrm{mp}2}$ of input transistors MP1 and MP2, respectively. The cross-coupled pairs MN1 and MN2 become active once the voltages at nodes X and Y reach the threshold voltage $V_{\mathrm{THN}}$. The positive feedback around these transistors eventually brings one output back to $V_{\mathrm{SS}}$ while allowing the other to rise to $V_{\mathrm{DD}}$.

Assuming that MN1 and MN2 are in the saturation region, draw an equivalent circuit diagram as shown in Figure 2. Writing a KCL at the node X gives

$$C_{\mathrm{p}}{\displaystyle \frac{\mathrm{d}{v}_{\mathrm{X}}}{\mathrm{d}t}}+{\displaystyle \frac{v_{\mathrm{X}}}{r_{\mathrm{o}}}}+g_{\mathrm{mn}}{v}_{\mathrm{Y}}=0,$$

(3)

Similarly, we have at the node Y

$$C_{\mathrm{p}}{\displaystyle \frac{\mathrm{d}{v}_{\mathrm{Y}}}{\mathrm{d}t}}+{\displaystyle \frac{v_{\mathrm{Y}}}{r_{\mathrm{o}}}}+g_{\mathrm{mn}}{v}_{\mathrm{X}}=0,$$

(4)

Our analysis is simplified if we only consider the differential output. The differential output can be expressed as

$$v_{\mathrm{XY}}=v_{\mathrm{X}}-v_{\mathrm{Y}},$$

(5)

Subtracting formula 4 from formula 3 yields

$$C_{\mathrm{p}}{\displaystyle \frac{\mathrm{d}{v}_{\mathrm{XY}}}{\mathrm{d}t}}+{\displaystyle \frac{v_{\mathrm{XY}}}{r_{\mathrm{o}}}}-g_{\mathrm{mn}}{v}_{\mathrm{XY}}=0,$$

(6)

We thus have

$$v_{\mathrm{XY}}=v_{\mathrm{XY}0}\exp \left({\displaystyle \frac{t}{\frac{r_{\mathrm{o}}{C}_{\mathrm{p}}}{g_{\mathrm{mn}}{r}_{\mathrm{o}}-1}}}\right),$$

(7)

where $r_{\mathrm{o}}$ is the output resistance of the node X and Y. Assuming $g_{\mathrm{mn}}{r}_{\mathrm{o}}\gg 1$, formula 7 can be re-written as

$$v_{\mathrm{XY}}\approx v_{\mathrm{XY}0}\exp \left({\displaystyle \frac{t}{\frac{C_{\mathrm{p}}}{g_{\mathrm{mn}}}}}\right),$$

(8)

Substituting formula 2 into formula 8 yields

$$v_{\mathrm{XY}}={\displaystyle \frac{V_{\mathrm{THN}}{C}_{\mathrm{p}}}{I_{\mathrm{CM}}}}{g}_{\mathrm{mp}}(v_{\mathrm{IP}}-v_{\mathrm{IN}})\exp \left({\displaystyle \frac{t}{\frac{C_{\mathrm{p}}}{g_{\mathrm{mn}}}}}\right),$$

(9)

Assuming the final output voltage is $v_{\mathrm{XY}}(\infty )$, the regeneration time $t_2$ can be calculated as

$$t_2={\displaystyle \frac{C_{\mathrm{p}}}{g_{\mathrm{mn}}}}ln\left({\displaystyle \frac{v_{\mathrm{XY}}(\infty )I_{\mathrm{CM}}}{V_{\mathrm{THN}}{C}_{\mathrm{p}}{g}_{\mathrm{mp}}{v}_{\mathrm{I}}}}\right),$$

(10)

where $v_{\mathrm{I}}$ is the differential input voltage, and equals to $v_{\mathrm{IP}}-v_{\mathrm{IN}}$.

Thus the total delay of the comparator can be given as

$$t_{\mathrm{d}}=t_1+t_2={\displaystyle \frac{V_{\mathrm{THN}}{C}_{\mathrm{p}}}{I_{\mathrm{CM}}}}+{\displaystyle \frac{C_{\mathrm{p}}}{g_{\mathrm{mn}}}}ln\left({\displaystyle \frac{v_{\mathrm{XY}}(\infty )I_{\mathrm{CM}}}{V_{\mathrm{THN}}{C}_{\mathrm{p}}{g}_{\mathrm{mp}}{v}_{\mathrm{I}}}}\right),$$

(11)

As demonstrated in formula 11, an increase in the common-mode current $I_{\mathrm{CM}}$ is associated with a decrease in the charging time $t_1$ and an increase in the regeneration time $t_2$. This occurs because a higher the common-mode current $I_{\mathrm{CM}}$ shortens the time needed for the parasitic capacitance to charge to a voltage close to the threshold voltage $V_{\mathrm{THN}}$. However, an increase in common-mode current also results in a decrease in the initial output voltage $v_{\mathrm{OUT}0}$, which in turn prolongs an increase in the regeneration time $t_2$.

The transconductance $g_{\mathrm{m}}$ of MOS can be expressed as

$$g_{\mathrm{m}}=\sqrt{2\mu C_{\mathrm{ox}}{\displaystyle \frac{W}{L}}{I}_{\mathrm{D}}}=\sqrt{2\mu C_{\mathrm{ox}}{\displaystyle \frac{W}{L}}{I}_{\mathrm{CM}}},$$

(12)

where $\mu$ denotes the electron mobility of MOS, $C_{\mathrm{ox}}$ represents the gate-oxide capacitance per unit area for MOS. As can be seen from formula 12, increasing the common-mode current $I_{\mathrm{CM}}$ can increase the transconductance $g_{\mathrm{m}}$ while maintaining the same dimensions of MOS.

Substituting formula 12 into formula 11 yields

$$t_{\mathrm{d}}={\displaystyle \frac{V_{\mathrm{THN}}{C}_{\mathrm{p}}}{I_{\mathrm{CM}}}}+{\displaystyle \frac{C_{\mathrm{p}}}{\sqrt{2{\mu }_{\mathrm{n}}{C}_{\mathrm{ox}}{\left(\frac{W}{L}\right)}_{\mathrm{n}1,2}{I}_{\mathrm{CM}}}}}ln\left({\displaystyle \frac{v_{\mathrm{XY}}(\infty )}{V_{\mathrm{THN}}{C}_{\mathrm{p}}{v}_{\mathrm{I}}}}\sqrt{{\displaystyle \frac{I_{\mathrm{CM}}}{2{\mu }_{\mathrm{p}}{C}_{\mathrm{ox}}{\left(\frac{W}{L}\right)}_{\mathrm{p}1,2}}}}\right),$$

(13)

As shown in Figure 3, the MATLAB simulation indicates that as the common-mode current increases, the delay $t_{\mathrm{d}}$ of the comparator decreases. It is evident that when the common-mode current is increased from 50 $\mu \mathrm{A}$ to 200 $\mu \mathrm{A}$, the delay decreases significantly. However, with further increase in common-mode current, the reduction in delay time becomes progressively smaller. This phenomenon can be attributed to the substantial reduction in regeneration time $t_2$ that is caused by the increase in common-mode current. Although the charge time $t_1$ also decreases, this decrease is negligible. As the common-mode current continues to increase, the regeneration time $t_2$ gradually approaches a a fixed lower bound.

However, excessively large common-mode currents pose a significant challenge for circuit design. Assuming both MP1 and MP2 are in the saturation region, the common-mode current can be written as

$$I_{\mathrm{CM}}={\displaystyle \frac{1}{2}}{\mu }_{\mathrm{p}}{C}_{\mathrm{ox}}{\left({\displaystyle \frac{W}{L}}\right)}_{\mathrm{p}1,2}{(V_{\mathrm{CM}}-V_{\mathrm{S}}-V_{\mathrm{THP}})}^2,$$

(14)

where ${\mu }_{\mathrm{p}}$ denotes the electron mobility of MP1 and MP2, $C_{\mathrm{ox}}$ represents the gate-oxide capacitance per unit area for MP1 and MP2, $V_{\mathrm{CM}}$ and $V_{\mathrm{S}}$ are the input common-mode voltage and the source voltage of MP1 and MP2, respectively. And $V_{\mathrm{THP}}$ is the threshold voltage of MP1 and MP2. According to formula 14, two challenges are apparent in circuit design. Firstly, excessive common-mode current requires larger input transistors. Oversized input transistor not only increase the layout area but also enlarge gate-drain parasitic capacitance, which increases the output load. Secondly, comparators must operate over a range of input common-mode voltages. Since the common-mode current is proportional to the square of the input common-mode voltage, any variation in the input common-mode voltages directly changes the common-mode current, thereby altering the delay time of the comparator. Excessively high or low common-mode voltages can cause malfunctions in comparators.

As demonstrated in the preceding analysis, it can be observed that the delay of the comparator depends on the common-mode current $I_{\mathrm{CM}}$. It is clear that simply increasing the size of the input transistor is not the optimal approach, as parasitic capacitance increases with the size of the input transistor. This increased capacitance leads to an increase in delay and power consumption of the comparator. Furthermore, the delay of the comparator is sensitive to the common-mode voltage, and alternations in the common-mode voltage can result in substantial fluctuations in the delay.

2.2. Proposed Enhanced Dynamic Bias Comparator

It has been demonstrated that increasing the common-mode current can enhance the speed of the comparator. However, a trade-off between common-mode current and the size of the input transistor must be resolved. As shown in Figure 4, a proposed enhanced dynamic bias comparator is presented. To increase the common-mode current $I_{\mathrm{CM}}$, additional transistors MP4 and MP5 are introduced, which provides the required common-mode current while maintains a compact size. If the common-mode current contributed by the input transistor is negligible compared to that supplied by MP4 and MP5, then the dependence of the delay on the input common-mode voltage can also be minimized. To conserve power, a dynamic bias technique is employed [23], which turns off the bias of the comparator after the comparator has completed its comparison. The effect of dynamic bias on the delay time of the comparator is negligible with the only overhead being the additional logic circuitry required. The circuit is composed of two sections: the comparator and the logic circuit. In the logic circuit section, the comparator output signals $v_{\mathrm{OP}}$ and $v_{\mathrm{ON}}$ pass through an XOR gate and a inverter, and then combined with the clock CK via a NAND gate to generate the final control signal fnh. The main purpose of the control signal fnh is to dynamically enable or disable the comparator, thereby reducing power consumption.

When the clock CK is low, the comparator is in the reset state. The control signal fnh is high, causing MP3, MP4 and MP5 to turn off, MN3 to turn on, and the comparator is disable. At the same time, MN3 connects nodes X and Y to equalize the voltages $v_{\mathrm{X}}$ and $v_{\mathrm{Y}}$. And the output $v_{\mathrm{OP}}$ and $v_{\mathrm{ON}}$ are reset to zero in the latch.

When the clock CK transitions from low to high, the comparator begins operation. The control signal fnh transitions from high to low, causing MP3, MP4 and MP5 to turn on while MN3 turns off. The additional current provided by MP4 and MP5 charges nodes X and Y. Simultaneously, the common-mode current from MP1 and MP2 also charges nodes X and Y. During this process, the input signals $v_{\mathrm{IP}}$ and $v_{\mathrm{IN}}$ provide differential current to nodes X and Y through MP1 and MP2. This stage is referred to as the charging phase of the comparator.

The cross-coupled pairs MN1 and MN2 becomes active once the voltages at nodes X and Y reach the threshold voltage $V_{\mathrm{THN}}$. The positive feedback around these transistors eventually brings one output back to zero while allowing the other to rise to $V_{\mathrm{DD}}$. Subsequently, the latch stores the outputs of the comparator and pass them to the subsequent stage.

Once the output is settled, the output voltages $v_{\mathrm{OP}}$ and $v_{\mathrm{ON}}$ are always at complementary levels ($V_{\mathrm{DD}}$ and $V_{\mathrm{SS}}$, respectively). Consequently, the control signal fnh transitions from a low level to a high level, disabling the bias of the comparator and reducing its dynamic power consumption. When the clock CK goes low, the comparator and the latch re-enter the reset state. Voltages $v_{\mathrm{OP}}$ and $v_{\mathrm{ON}}$ are reset to zero, while voltages $v_{\mathrm{X}}$ and $v_{\mathrm{Y}}$ are reset to near the threshold voltage $V_{\mathrm{THN}}$. As the clock CK is low, the control signal fnh remains high, waiting for the next enable cycle.

The proposed enhanced dynamic bias comparator offers two main advantages. First, the addition of auxiliary current paths accelerates the speed of the comparator. Second, dynamic bias of the comparator is achieved through the implementation of simple logic circuits. This reduces the power consumption of the comparator, thereby enhancing its overall energy efficiency.

3. Design of the Offset Calibration Technique

3.1. Working Principle of the Comparator

As shown in Figure 5, the circuit diagram and timing diagram of a comparator with offset for voltage comparison is presented. During the sampling phase, the clock ${\phi }_1$ is high, while the clock ${\phi }_2$ is low. The top plates of sampling capacitors $C_{\mathrm{sp}}$ and $C_{\mathrm{sn}}$ are connected to the common-mode voltage $V_{\mathrm{CM}}$, while their bottom plates are connected to the input signals $v_{\mathrm{IP}}$ and $v_{\mathrm{IN}}$, respectively. At time $t_0$, the voltage across the sampling capacitor can be written as

$$v_{\mathrm{csp}}\left(t_{0-}\right)=V_{\mathrm{CM}}-v_{\mathrm{IP}}\left(t_{0-}\right),$$

(15)

$$v_{\mathrm{csn}}\left(t_{0-}\right)=V_{\mathrm{CM}}-v_{\mathrm{IN}}\left(t_{0-}\right),$$

(16)

During the comparison phase, the clock ${\phi }_1$ goes low, while the clock ${\phi }_2$ goes high. The bottom of sampling capacitors $C_{\mathrm{sp}}$ and $C_{\mathrm{sn}}$ are connected to the reference signals $V_{\mathrm{RP}}$ and $V_{\mathrm{RN}}$, respectively. At time $t_1$, the comparator begins operation. At this moment, the voltages at nodes X and Y can be expressed as

$$v_{\mathrm{X}}\left(t_{1-}\right)=v_{\mathrm{csp}}\left(t_{0-}\right)+V_{\mathrm{RP}},$$

(17)

$$v_{\mathrm{Y}}\left(t_{1-}\right)=v_{\mathrm{csn}}\left(t_{0-}\right)+V_{\mathrm{RN}}+V_{\mathrm{OS}},$$

(18)

Subtracting formula 17 from formula 18, the input differential voltage of the comparator can be expressed as

$$\begin{array}{cc}\hfill v_{\mathrm{I},\mathrm{cmp}}\left(t_{1-}\right)& =v_{\mathrm{Y}}\left(t_{1-}\right)-v_{\mathrm{X}}\left(t_{1-}\right)\hfill \\ \hfill & =(v_{\mathrm{IP}}\left(t_{0-}\right)-v_{\mathrm{IN}}\left(t_{0-}\right))-(V_{\mathrm{RP}}-V_{\mathrm{RN}})+V_{\mathrm{OS}},\hfill \end{array}$$

(19)

The supplementary equation is as follow

$$v_{\mathrm{I}}\left(t_{0-}\right)=v_{\mathrm{IP}}\left(t_{0-}\right)-v_{\mathrm{IN}}\left(t_{0-}\right),$$

(20)

$$V_{\mathrm{REF}}=V_{\mathrm{RP}}-V_{\mathrm{RN}},$$

(21)

Substituting formula 20 and formula 21 into formula 19, yields

$$v_{\mathrm{I},\mathrm{cmp}}\left(t_{1-}\right)=v_{\mathrm{I}}\left(t_{0-}\right)-(V_{\mathrm{REF}}-V_{\mathrm{OS}}),$$

(22)

From formula 22, it is evident that the presence of the offset voltage $V_{\mathrm{OS}}$ results in a shift of the reference comparison point of the comparator by an amount equivalent to $-V_{\mathrm{OS}}$. If the offset voltage of the comparator is large, it will have a detrimental effect on the performance of the analog-to-digital converter.

3.2. Proposed Reference-Compensated Offset Calibration Technique

As shown in Figure 6, the schematic diagram of the comparator with reference-compensated technique is presented. The alteration of reference voltage at the comparison point serves as a method to compensate for the offset voltage of the comparator. When the reference voltage is changed, formula 22 can be rewritten as

$$v_{\mathrm{I},\mathrm{cmp}}\left(t_{1-}\right)=v_{\mathrm{I}}\left(t_{0-}\right)-V_{\mathrm{REF}}-(\Delta V-V_{\mathrm{OS}}),$$

(23)

From formula 23, it can be seen that when $\Delta V$ equals $V_{\mathrm{OS}}$, the offset voltage of the comparator can be eliminated. The step size of $\Delta V$ is directly proportional to the precision of the calibration. Higher calibration accuracy corresponds to a smaller step size of $\Delta V$, whereas lower accuracy requires a larger step size of $\Delta V$.

As illustrated in Figure 7, the schematic diagram of the proposed calibration scheme is presented. The entire calibration circuit consists of four sections: the comparator under calibration, the voltage generation circuit, the counter and the digital logic control circuit. At the start of calibration, the sampling capacitor is connected to the reference voltage $V_{\mathrm{RP}}$ and $V_{\mathrm{RN}}$ via the clock ${\phi }_1$ during sampling phase, rather than to the input signals $v_{\mathrm{IP}}$ and $v_{\mathrm{IN}}$. The sampling capacitor is connected to the reference voltage with a compensation offset $\alpha V_{\mathrm{c}}$ via the clock ${\phi }_2$ during comparison phase. The calibration voltage $V_{\mathrm{c}}$ represents the step size of $\Delta V$ and is directly proportional to the calibration accuracy. $\alpha$ is a multiple of 1/2, and in this design, it takes nine values: -2, -3/2, -1, -1/2, 0, 1/2, 1, 3/2, and 2. The digital control logic commands the voltage-generation circuit to adjust the compensation level of the reference voltage. Simultaneously, the counter collects the output of the comparator ot estimate the offset magnitude.Ultimately, the compensation of the reference voltage is adjusted to an appropriate level, reducing the offset voltage $V_{\mathrm{OS}}$ to a system-acceptable value.

The control logic circuit is driven by the digital clock dclk. When the falling edge of the reset signal rst arrives, the offset calibration process of the comparator starts. If the calibration-enable signal cal is 1, the calibration circuit proceeds to the next stage; if it is 0, calibration ends. The control word co generated by the control logic is sent simultaneously to the voltage generation circuit and the counter. The default value of co is 1. The voltage generation circuit adjusts the coefficient $\alpha$ from -2 to 2 based on the control word co ranging from 1 to 9. The counter increment is based on the current output result. The counter increments only when the comparator output dop is 1. After completing avg comparisons and counts, the algorithm determines the compensation point that exhibits the minimum offset voltage. This compensation point is then designated as the reference comparison point for the normal operation of the comparator.

In conventional pipelined ADC, the reference comparison point of the comparator is obtained from a resistive voltage divider. The voltage generation circuit can be realized by segmenting the original resistor string into smaller equal-valued resistors, thereby introducing additional reference-compensation points around the nominal comparison point. The main advantage of this approach is that it avoids extra analog circuitry, which reduces both the hardware overhead and the power consumption typically incurred by analog calibration circuits.

The reference-compensated offset calibration technique proposed in this paper achieves offset calibration for comparators without altering their structure. The analog circuit requires only a small number of additional voltage-division resistors, making this technique well-suitable for offset calibration of comparators in most pipelined ADCs.

4. Results

Figure 8 shows the typical waveforms of the proposed comparator. The simulation conditions are as follows: a supply voltage of 1.8 V, a common-mode voltage of 0.9 V, an input differential voltage of 100 mV, an operating frequency of 150 MHz, and a comparator load of 5 fF. When the rising edge of the clock CK arrives, the output voltage $v_{\mathrm{OP}}$ and $v_{\mathrm{ON}}$ develop a voltage difference of about 0.9 V within 190.3 ps. Approximately 300 ps later, the control signal fnh goes high, disabling the bias of the comparator to reduce its power consumption.

As shown in Figure 9a, the delay time of the comparator versus the differential input voltage is depicted at a fixed common-mode voltage of 0.9 V. At the differential input voltage of 0.1 mV, the proposed comparator has a delay of about 298 ps, while the conventional comparator has a delay of approximately 387 ps, which is roughly 89 ps longer. This indicates a significant advantage of the proposed comparator when processing very small input signals. Furthermore, the proposed comparator exhibits a delay time variation of approximately 115 ps over the entire differential input voltage range, compared to 172 ps for the conventional comparator, indicating that the conventional comparator has a 57 ps greater variation in delay time. These results demonstrate that the proposed comparator maintains excellent stability even under wide variations in the differential input voltage.

As shown in Figure 9b, the energy consumption of the comparator is plotted against the differential input voltage at a common-mode voltage of 0.9 V. At a differential input voltage of 0.1 mV, the energy consumption of the proposed comparator is 419 fJ/comparison, compared to 778 fJ/comparison for the conventional comparator. At 200 mV input, the corresponding values are 320 fJ/comparison and 536 fJ/comparison, respectively. These results indicated that the proposed comparator has a lower delay while consuming the same amount of energy. This is facilitated by the application of dynamic bias, which minimises the dynamic power consumption of the proposed comparator.

As shown in Figure 10a, the delay time of the comparator varies with changes in the common-mode voltage is plotted for the differential input voltage of 0.1 V. At a common-mode voltage is 0.7 V, the proposed comparator has a delay time of 185 ps. The delay increases gradually with the common-mode voltage, reaching 200 ps at 1.1 V. Over the entire common-mode voltage range, the delay variation of the proposed comparator is only about 15 ps. In contrast, the conventional comparator show a delay of 186 ps at 0.7 V. Its delay increases rapidly as the common-mode voltage rises, reaching a maximum of 390 ps at 1.1 V. The overall delay variation of the conventional comparator across the same range is about 204 ps, approximately 13 times larger than that of the proposed one. These results indicate that the proposed comparator maintains excellent performance under common-mode voltage variations, whereas the traditional comparator is significantly affected by changes in the common-mode voltage.

As shown in Figure 10b, the energy consumption of the comparator is plotted against the common-mode voltage at a differential input voltage of 0.1 V. At a common-mode voltage of 0.7 V, the energy consumption of the proposed comparator is 352 fJ/comparison, compared to 1116 fJ/comparison for the conventional one – a larger difference of 764 fJ/comparison. As the common-mode voltage increases, the energy consumption of both comparators decreases. At a common-mode voltage of 1.1 V, the energy consumption of the proposed comparator is 299 fJ/comparison, while the conventional comparator consumes 296 fJ/comparison, resulting in a much smaller difference of only 3 fJ/comparison. More importantly, over the entire common-mode voltage range, the proposed comparator exhibits a much smaller variation of 53 fJ/comparison in energy consumption, compared to 820 fJ/comparison for the conventional comparator. These results demonstrate that the proposed comparator maintains highly stable energy efficiency across common-mode voltage variations.

A Monte Carlo simulation is performed on the comparator with the common-mode voltage set to 0.9 V. The calibration step size is 15.6 mV, and the coefficients $\alpha$ takes the values: -2, -3/2, -1, -1/2, 0, 1/2, 1, 3/2, and 2. Figure 11 presents the results of 3600-sample Monte Carlo simulation under PVT (process, voltage, temperature) variations. The offset voltage of the comparator is reduced from 18.1 mV before calibration to 6.3 mV after calibration – an improvement of 11.8 mV. As shown in Figure 12, the Monte Carlo simulation of 400-sample under TT process reveals that, before calibration, the offset voltage shows significant dispersion, with a maximum value of around 60 mV. However, after calibration, the offset voltage is constrained between approximately ± 15.6 mV, which demonstrates that the calibration technique enhances the mismatch performance of the comparator.

Table 1 compares the performance of the proposed comparator with other comparators. Fabricated the same process technology, the proposed comparator achieves a significant speed advantage, with a delay time of 190.3 ps, compared to a minimum delay time of 268 ps in other works. Compared to other comparators, the proposed comparator shows advantages in terms of power consumption. However, there is still significant room for improvement in the power consumption. Thanks to the application of offset calibration technique, the proposed comparator achieves a offset voltage of just 6.3 mV. This indicates that there is further potential for optimization in its algorithm and structure.

5. Conclusions

This paper proposes an enhanced dynamic bias comparator and employs a novel reference-compensated offset calibration technique. First, the delay of the comparator is analyzed and validated through MATLAB simulation, revealing its depends on the common-mode current. Based on this insight, a enhanced structure is introduced, which not only increases the speed of the comparator but also mitigates the impact of common-mode voltage variations on the delay. Then, a dynamic bias is applied to reduce the dynamic power consumption of the comparator. Furthermore, to address comparator mismatch, a reference compensation technique is proposed to improve mismatch performance without altering the structure of the comparator.