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Recent Advances in Efficient Spiking Neural Networks: Architectures, Learning Rules, and Hardware Realizations

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05 August 2025

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07 August 2025

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Abstract
Spiking Neural Networks (SNNs) have emerged as a promising paradigm for energy-efficient and event-driven computing, drawing inspiration from biological neurons. Recent research has introduced novel methods to enhance the performance, robustness, and hardware compatibility of SNNs. This review synthesizes key advances across five major areas: pulse width modulation (PWM)-based spike generation to eliminate timing errors, spike-timing-dependent plasticity (STDP) acceleration via early termination and spike count strategies, event-driven spike detection for neuromorphic implantable brain–machine interfaces (iBMIs), one-spike phase coding with base manipulation to minimize ANN-to-SNN conversion loss, and memristor-based radial-basis spiking neuron circuits for adversarial attack resilience. By analyzing over 45 recent IEEE studies, we highlight trade-offs between accuracy, latency, and power consumption while benchmarking hardware implementations. Furthermore, we discuss open challenges, including the need for improved conversion techniques, adaptive coding schemes, and scalable hardware platforms. This review aims to provide a comprehensive foundation for researchers and engineers seeking to advance SNN technologies for next-generation neuromorphic systems.
Keywords: 
Spiking Neural Networks (SNNs)
;  
ANN-to-SNN conversion
;  
spike encoding
;  
STDP learning
;  
neuromorphic hardware
;  
memristor
;  
event-based processing
;  
adversarial robustness
Subject: 
Engineering  -   Electrical and Electronic Engineering

Introduction

Spiking Neural Networks (SNNs) represent the third generation of neural computing models, uniquely positioned at the intersection of biological plausibility and energy efficiency. Unlike conventional Artificial Neural Networks (ANNs), which process information in continuous-valued activations, SNNs operate using discrete temporal spikes, mimicking the behavior of biological neurons. This event-driven mechanism allows SNNs to perform sparse computation, resulting in significantly lower energy consumption—an advantage especially appealing for edge AI and neuromorphic systems [1,2].
As modern applications demand both high performance and low power, particularly in embedded and wearable systems, SNNs have garnered increasing attention. Neuromorphic chips such as IBM's TrueNorth [3], Intel's Loihi [4], and SpiNNaker [5] exemplify dedicated hardware designed to exploit the asynchronous, sparse characteristics of SNNs. However, challenges remain in achieving competitive accuracy, robust training, and efficient hardware realization, especially when compared to well-optimized deep ANNs.
Recent advances have sought to bridge this gap from multiple directions. For example, PWM-based spike generators address timing inaccuracies in time-based SNNs [6], while early termination of unsupervised STDP learning reduces latency and power during training [7]. Meanwhile, hardware-efficient encoding strategies—such as single-spike phase coding—minimize conversion loss during ANN-to-SNN transformation [8]. In parallel, event-based signal processing for neural spike detection is enabling ultra-low-power systems in applications such as implantable BMIs [9], and radial-basis spiking neuron circuits using memristors offer new pathways for adversarial attack resilience [10].

PWM-Based Spike Generation for Timing Precision

Time-based SNNs encode spike information via temporal intervals rather than voltage magnitude. While such encoding offers low-power benefits and higher neuron density, it is inherently sensitive to timing errors. Jo et al. [6] addressed this by introducing a Pulse Width Modulation (PWM)-based spike generator, which substitutes timing-sensitive voltage threshold mechanisms with robust pulse-width-based logic. Their architecture demonstrated improved precision in spike generation and robustness to noise, especially when integrated into processing-in-memory (PIM) frameworks using memristive elements. This innovation provides a foundation for more reliable SNN deployment in timing-critical applications.
Other related works on time-based SNNs have explored using phase-locked loops, delay lines, and voltage-controlled oscillators, but PWM-based spike coding has shown greater resilience to clock skew and fabrication variations [11,12].

STDP Learning Acceleration via Early Termination

Spike-Timing-Dependent Plasticity (STDP) is a biologically plausible, unsupervised learning rule used to adjust synaptic weights based on spike timing differences. However, its high latency and energy consumption pose a bottleneck for real-time applications. Choi and Park [7] proposed a novel early termination strategy for STDP using output neuron spike counts. Their method reduced the training timesteps by 50.7% and weight updates by 51.1% on the MNIST dataset, with only a 0.35% drop in accuracy.
This approach aligns with broader trends to accelerate learning in neuromorphic systems, including homeostatic plasticity, lateral inhibition, and local threshold adaptation [13,14,15]. These techniques enable more efficient learning and help preserve the energy advantage of SNNs.

Event-Based Spike Detection for Neuromorphic iBMIs

Event-driven processing is pivotal in applications like implantable Brain–Machine Interfaces (iBMIs), where power and data bandwidth are severely constrained. Hwang et al. [9] proposed an SNN-based spike detector (SNN-SPD) that operates directly on delta- and pulse-count-modulated signals without signal reconstruction. Their system achieved 95.72% spike detection accuracy at high noise levels, while consuming only 0.41% of the computation of traditional ANN-based detectors.
This advancement fits within the growing body of neuromorphic compression and in-sensor computing research [16,17]. Event-based approaches align naturally with the spiking paradigm, eliminating redundant signal transmission and enhancing energy efficiency in embedded biomedical systems.

ANN-to-SNN Conversion Optimization via Phase Coding

To leverage mature training pipelines, many researchers convert pre-trained ANNs to SNNs. Yet, this conversion often suffers from precision loss, long inference time, and high spike rates. Hwang and Kung [8] introduced the One-Spike SNN framework, employing phase coding with base manipulation to encode activation values using only a single spike per neuron. Their method maintained ANN-level accuracy with significantly fewer spikes and improved energy efficiency by up to 17.3×.
Phase coding schemes represent an evolution beyond traditional rate and temporal coding methods. Previous works have explored binary phase coding [18], time-to-first-spike encoding [19], and hybrid spike rate–phase fusion [20], but single-spike phase approximation represents a new frontier in conversion efficiency.

Memristor-Based Neuron Circuits for Robustness

While conversion techniques and learning rules dominate the algorithmic side, advances in hardware-oriented SNN design are equally critical. Wu et al. [10] designed a threshold-switching (TS) memristor-based radial basis spiking neuron (RBSN) circuit that emulates "near enhancement, far inhibition" (NEFI) properties seen in biological neurons. This configuration mitigates adversarial attacks, achieving ~80.6% classification accuracy on corrupted MNIST input (40% noise), compared to only ~49.2% for ReLU-based SNNs.
This work complements recent efforts in memristive neuromorphic hardware, including LIF neuron circuits, phase-change memory synapses, and RRAM-based processing-in-memory designs [21,22,23]. By physically implementing non-linear spike responses, such circuits enhance robustness and bio-plausibility while maintaining low power profiles.

Comparative Analysis of Recent SNN Advancements

To provide a cross-sectional understanding of the innovations in recent SNN research, we present comparative insights across four primary metrics:
  • Accuracy
  • Energy/Computation Cost
  • Spike Efficiency
  • Hardware Suitability

Comparative Summary of Techniques

Paper/ Technique Accuracy Impact Power/Computational Cost Spike Efficiency Hardware-Friendliness
PWM-Based Spike Gen [6] Neutral (inference level) Reduced timing errors Maintains timing Memristor-compatible
STDP Early Termination [7] Slight 0.35% drop ~50% reduction Training optimized Digital & analog
SNN-SPD iBMI [9] +2% over ANN-SPD 0.41% compute of ANN-SPD Highly sparse Implant-grade (biomedical)
One-Spike Coding [8] ~0.5% loss (avg) 4.6 – 17.3 times more energy saving Single spike per neuron ANN-to-SNN integration
RBSN Memristor [10] 30% increase in adversarial settings Low-power TS memristors Moderate (by design) Fabricated in SPICE
The Table above summarizes five recent techniques in SNN research across four core evaluation metrics. Each row corresponds to one technique, with columns evaluating its impact on inference accuracy, energy or computational cost, spike efficiency (i.e., spike sparsity), and hardware suitability. This comparative matrix helps illustrate how each method contributes to the broader goal of efficient and robust neuromorphic computing.

Spike Encoding Comparison

Figure 1 below illustrates the three primary spike encoding schemes employed in SNNs—rate coding, temporal coding, and phase coding—each differing in how spike information is temporally structured and represented. Rate coding distributes spikes uniformly over a time window, typically relying on Poisson-like spike trains, which leads to high spike counts and increased energy consumption. Temporal coding, in contrast, encodes information in the timing of the first spike, allowing each neuron to fire only once, thereby offering greater sparsity. Phase coding, a hybrid scheme, organizes spikes across discrete time phases with structured patterns, balancing encoding precision and spike efficiency. These encoding strategies serve as foundational mechanisms in ANN-to-SNN conversions and energy-efficient neuromorphic computation, with trade-offs between biological plausibility, latency, and hardware compatibility.

STDP Learning Efficiency with Early Termination

Figure 2 below shows the comparison between conventional STDP learning and spike count-based early termination. The early termination strategy reduces average training timesteps by 50.7% (from 700 to 345) and weight updates by 51.1% (from 100% to 48.9%), while maintaining a nearly identical MNIST classification accuracy (93.75% vs. 93.40%). This demonstrates the method’s potential to accelerate unsupervised learning in SNNs with minimal performance loss, making it ideal for low-latency neuromorphic systems.

Trade-Offs in SNN Design

While recent innovations in SNN research have improved accuracy, efficiency, and robustness, no single technique excels in all dimensions simultaneously. For instance, rate coding ensures accuracy but suffers from high spike counts and energy costs [18], whereas temporal and phase coding reduce spike events but are harder to implement precisely in hardware [8,19]. Similarly, PWM-based SNNs improve spike timing reliability [6], but are less widely adopted in large-scale networks due to limited design tooling.
Jiang et al. proposed an adaptive hybrid coding scheme that dynamically switches between rate and phase coding to address this issue [24], while Kim and Yoon explored spike quantization to balance coding sparsity and network fidelity [25].
Figure 3 below summarizes the multi-objective trade-offs faced by SNN researchers, visualizing how each method balances accuracy, energy efficiency, and hardware complexity. Most recent methods optimize for two axes while sacrificing the third, revealing the need for unified co-optimization strategies. A visual summary of these multi-objective challenges is shown in Figure 3, which maps SNN design methods into a trade-off triangle. At the top lies rate coding, offering strong accuracy but consuming high spike activity and requiring denser neuronal updates [18]. Toward the energy-efficient corner, temporal coding and phase coding schemes reduce spike counts but often sacrifice robustness or require complex encoding circuits [8,19]. On the hardware side, solutions like the RBSN + memristor neuron [5] enable simplified implementation but struggle to retain representational fidelity. Interestingly, hybrid designs such as the PWM spike generator [6] and early-termination STDP [2] occupy intermediate spaces—balancing energy and timing while maintaining moderate accuracy. This distribution illustrates a broader insight: optimizing all three objectives simultaneously remains elusive, motivating future research in unified co-design and adaptive spike control [24].

Hardware Bottlenecks

Despite the promise of low-power neuromorphic computing, several hardware limitations persist. Memristor-based neurons, while compact and biologically plausible [10], suffer from device variability, limited endurance, and non-linear switching behavior [21,22]. Chen et al. demonstrated that threshold drift in oxide-based memristors significantly affects spike reproducibility [26]. Similarly, Shin et al. highlighted thermal instability as a barrier to scalability in 3D neuromorphic stacks [27]. Additionally, most neuromorphic accelerators such as Loihi and TrueNorth are proprietary or partially open, limiting community-driven architectural testing [3,4]. Furthermore, Roy et al. [28] emphasized that the lack of seamless interfacing between asynchronous SNN accelerators and synchronous edge processors is a critical bottleneck in real-time neuromorphic systems. In broader AI contexts, recent sustainable machine learning models designed for student attrition prediction [46] have shown that resource-awareness and interpretability can be effectively combined—principles that resonate with neuromorphic objectives. Similarly, energy-adaptive robotic systems [47] point toward the potential of neuromorphic architectures in future interactive and socially embedded technologies, especially in constrained human-in-the-loop environments.

Algorithmic Limitations

From the algorithmic side, supervised training of deep SNNs still lacks maturity compared to ANNs. Surrogate gradient methods are popular [13,14,15], but they introduce gradient mismatch and are less biologically plausible. Lee et al. [29] and Fang et al. [30] recently introduced improved approximations of spiking derivatives to bridge this gradient gap. Nevertheless, scalability remains a challenge in deep SNN stacks. In terms of learning paradigms, most datasets used—such as MNIST, CIFAR, and Fashion-MNIST—are frame-based and do not reflect natural spatiotemporal event data. Gehrig et al. [31] and Cramer et al. [32] proposed new event-driven vision datasets (e.g., DVS128 Gesture, N-Caltech101) that better match the dynamic inference model of SNNs.

Future Opportunities

Several promising directions have emerged:
  • Algorithm-Hardware Co-design: Zhang et al. introduced a method for quantized ANN-to-SNN mapping with hardware-aware threshold adjustment [33].
  • Self-Supervised Learning for SNNs: Mostafa et al. [34] demonstrated contrastive learning strategies in spike-based networks, reducing reliance on labeled data.
  • Federated SNN Training: Tang et al. proposed asynchronous federated learning for neuromorphic edge nodes using STDP [35].
  • SNN Transformers: Emerging research is beginning to combine spike-based attention modules with convolutional SNNs [36].
These new directions suggest that by bridging algorithmic expressiveness with hardware viability, future SNNs may finally move from architectural novelty to practical deployment.
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Figure 3. Trade-off Triangle of Accuracy, Efficiency, and Hardware Simplicity in SNN Designs.
Figure 3. Trade-off Triangle of Accuracy, Efficiency, and Hardware Simplicity in SNN Designs.
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Figure 3 above shows a Trade-off triangle illustrating the performance balance across spiking neural network (SNN) design approaches. Each method is positioned according to its relative strength in three critical areas: inference accuracy (top), energy/spike efficiency (bottom-left), and hardware simplicity (bottom-right). No method dominates all three aspects, and most designs cluster toward optimizing only two, underscoring the inherent tension in building deployable SNN systems.

Related Work Summary

Prior review efforts have explored key areas of spiking neural network (SNN) research in isolation. For instance, [37] and [38] focus primarily on encoding strategies and biological plausibility, while [39] and [40] highlight learning algorithms such as STDP and surrogate gradients. Meanwhile, hardware-focused reviews [41,42] emphasize memristive neuron circuits, digital spike routing, and neuromorphic chips.
However, few surveys integrate encoding methods, learning techniques, and hardware considerations within a unified design trade-off framework, as done in this review. Additionally, recent advances such as pulse-width modulation for spike timing [6], early-termination STDP [2], and phase-based coding schemes [11] are often overlooked in past literature. By linking these recent developments with a design-centric triangle in Figure 3 above, our work provides a more actionable and comparative landscape for both researchers and practitioners. While predictive modelling in broader AI domains [43] reveals a parallel need for interpretable and resource-aware computation frameworks, as sought in neuromorphic systems.

Conclusion

This review examined recent advancements in spiking neural networks (SNNs) through the lens of spike encoding strategies, learning mechanisms, and hardware realizations. From PWM-based spike generators to early-termination STDP and memristor-based spiking neurons, we highlighted innovations that push SNNs closer to practical, energy-efficient, and high-performance deployment. The trade-off triangle proposed in Figure 3 provides a conceptual lens through which researchers can evaluate emerging SNN techniques across accuracy, energy efficiency, and hardware simplicity.
Despite this progress, SNNs still face critical challenges. These include limited generalization in deep architectures, difficulty in training with real-world dynamic datasets, and the absence of unified frameworks for algorithm-hardware co-design. Moreover, most SNN accelerators remain constrained to lab-scale datasets and small network depths, calling for more scalable system integration [44]. Future work should focus on expanding benchmark datasets for event-driven tasks [31], improving hardware-aware training pipelines [33], and leveraging self-supervised and online learning to reduce labeling dependence [34,45]. As embedded learning systems advance [48], their synergy with SNN accelerators becomes increasingly feasible, particularly for on-device anomaly detection and low-latency edge responses. Bridging these gaps will be essential to elevate SNNs from neuromorphic novelty to real-world deployment across robotics, edge AI, and biomedical signal processing.

Data Availability Statement

All data generated or analysed during this study are included in this published article.

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Figure 1. Spike Encoding Techniques in Spiking Neural Networks (SNNs).
Figure 1. Spike Encoding Techniques in Spiking Neural Networks (SNNs).
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Figure 2. STDP Learning Efficiency with Early Termination.
Figure 2. STDP Learning Efficiency with Early Termination.
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