A High-Efficiency Frequency Multiplier with Triangular-Resistance Phase Interpolation

1. Introduction

Frequency multipliers are widely utilized in communication systems to generate high-frequency working clocks from a low-frequency reference one. The traditional mechanisms for achieving frequency multiplication can be broadly divided into two categories. One is to use a nonlinear device or a narrow-pulse generator for harmonic generation and then employ a bandpass filter to extract the desired harmonic frequency [1,2,3,4], but encounters a limited multiplication factor or a complex filtering topology. The other is to use digital sub-sampling / injection-locked phase-locked loops (PLLs) based on frequency discrimination and division, to get a higher output frequency from the embedded voltage-controlled oscillator (VCO) under the reference of a lower input frequency, which has a pure output spectrum and low output noise, at the cost of the hardware implementation [5,6,7].

An optimized method is to inject the harmonics into a free-running oscillator or quadrupler [8,9], however, the injection-locked frequency multipliers suffer from a limited frequency range, and additional error-correcting modules are required. Nowadays, the mainstream frequency multipliers [10,11,12,13] consist of a multiphase generator and an edge combiner, and employ a delay-locked loop or a RC network or a multiphase VCO. However, these popular mechanisms either have poor robustness or require complex loops.

In this Article, a high-efficiency five-segment triangular-resistance phase interpolation (TRPI) scheme is proposed, which is fully different from the existing literature. As a result, a low-power, low-cost and configurable frequency multiplier is achieved.

This Article is organized as follows: Section 2 gives the frequency multiplier architecture, and Section 3 gives the detailed circuit implementation, followed by the experimental results in Section 4 and conclusion given in Section 5.

Figure 1. Proposed frequency multiplier: (a) low-cost architecture, and (b) triangular-resistance phase interpolation scheme with k=5.

Figure 1. Proposed frequency multiplier: (a) low-cost architecture, and (b) triangular-resistance phase interpolation scheme with k=5.

2. Proposed Architecture

A low-complexity frequency multiplier is proposed based on multiphase triangular generation and k-segment resistive phase interpolation scheme, which is shown in Figure 1(a). Four paths of quadrature clocks are provided by a square-wave generator with a frequency division of 2 from the input reference signal, and then are sent to four parallel square-to-triangular converters to get the orthogonal triangular signals. The subsequent phase interpolator based on 5-segment resistance across two adjacent triangular signals with a fixed phase difference of 90°, generates 4 groups of narrow pulses with a phase step of 18° (=90°/5). Therefore, four paths of quadrature interpolators get 4×5 groups of narrow pulses. Finally, all pulses are combined together in an OR gate to conduct frequency multiplication with a factor (n) as depicted in (1).

$$n={\displaystyle \frac{F_{out}}{F_{IN}}}={\displaystyle \frac{1}{2}}\times k\times 4=2k$$

(1)

The proposed mechanism could be extended to achieve a configurable multiplication factor, depending on the number (k) of interpolating resistors that are used. To accomplish a high multiplication robustness over different triangular-wave slopes, common-mode feedback (CMFB) modules are applied to the square-triangular converters, to achieve zero-crossing voltage (V_CM) calibration and benefit the subsequent V_CM comparison. To ensure an accurate phase step and relax the hardware complexity, the phase interpolation is conducted on triangular waves rather than other signal types such as sinusoidal or sawtooth waves.

Resistive interpolation technique is a simple, passive and high-efficiency method of various multiphase schemes. The operational principle of the proposed 5-segment resistive phase interpolation is shown in Figure 1(b). Five serial resistors with the same size are inserted between two adjacent triangular signals with a phase difference of 90°. Twenty same resistors in total are used in four paths of interpolators. The phase-interpolating voltages (V₁-V₅, V₆-V₁₀) and the corresponding waveforms are thus generated, which are evenly distributed at equal time (phase) intervals between orthogonal triangular signals. As a result, a small phase step of 18° (=90°/5) is achieved. With four paths of 5-segment resistive phase interpolators, 20 narrow pulses are generated with the adjacent pulse phase difference of 18°, and thus ten-fold frequency multiplication is finally done.

The proposed architecture only consists of a digital quadrature square-wave generator, four analogue orthogonal triangular converters and four digitalized phase interpolators, and is thus considered as a half-digital implementation. The presented topology has the following merits: 1) reconfigurable multiplication factor; 2) half-digital structure that benefits to low-cost low-power features; and 3) common-mode feedback and comparison optimize the frequency robustness and thus the multiplication efficiency.

3. Design Implementation

3.1. Low-Cost Quadrature Square-Wave Generator

The proposed multiplication mechanism requires multiphase clock signals for phase interpolation. A simplified square-wave generator is given in Figure 2, based on D-type flip-flops (DFFs) and logic gates to get four paths of quadrature signals. The edge detector doubles the input clock frequency (such as 16 MHz), by triggering both rising and falling edges via an inverter-based delay cell. The quadrature divider-by-4, is made of two-stage cascaded dividers-by-2, and conducts the frequency division of 4 to generate four paths of clocks with an accurate phase difference of 90° under the output frequency of 8 MHz. CMOS transmission gates (TGs) are adopted to match the inverter delay, to get an accuracy phase difference of 90°. The MOS capacitor is used to set the pulse width (8 ns) for the edge detector. CMOS transmission gates (TGs) are adopted to match the inverter delay, to get an accuracy phase difference of 90°. Due to the rising-edge trigger mode of DFFs, the initial timing order is different at the first arriving clock edge between rising and falling, which causes the output phase dislocation. To avoid this, the additional edge detector is introduced.

3.2. Low-Power Square-to-Triangular Converter

Since the proposed multiplication mechanism prefers for triangular waves, multiphase square-to-triangular converters are needed. Figure 3 shows the proposed converter based on capacitor charging-discharging scheme controlled by two pairs of complementary switches under the timing sequence of the differential square waves. The low-voltage cascode current mirror provides a fixed charging-discharging current (I_C) through the capacitor to generate a triangular wave.

To avoid the triangular distortions that happen at the peaks and valleys due to the level translation of square waves, a replica cell is introduced to guarantee the continuity of charging-discharging current. The triangular slope and peak / valley voltages (V_H / V_L) are depicted in (2). Here, T is the square-wave period. Low-voltage cascode topology ensures enough voltage-drop margins for V_H and V_L. That is, the presented converter not only has a high robustness over process / voltage / temperature (PVT) variations, but covers a wide input frequency range.

$$Slope={\displaystyle \frac{I_C}{C}},V_H=V_{CM}+{\displaystyle \frac{I_C}{C}}\times {\displaystyle \frac{T}{4}},V_L=V_{CM}-{\displaystyle \frac{I_C}{C}}\times {\displaystyle \frac{T}{4}}$$

(2)

Additionally, to match the phase-interpolating voltages (V₁-V₂₀) to V_CM, the CMFB module is introduced, accomplishing a high multiplication robustness over different slopes under PVT variations. After lowpass filtering, the triangular CM voltage is got and compared to V_CM, which inversely tunes the current I_F and thus corrects the triangular DC voltage. Considering the two-stage loop stability of the CMFB, a high-speed high-gain amplifier with a diode-connected cross-couple topology is used.

3.3. Digitalized Resistive Phase Interpolator

As the core module of the frequency multiplier, the presented triangular-resistance phase interpolators set the upper limit of both silicon area and power consumption. To achieve low cost / power, Figure 4 gives the proposed four-path quadrature 5-segment phase interpolators, with a digitalized and passive structure including 20 resistors, 20 simplified comparators, 20 MOS-transistor capacitors, and a small quantity of logic gates.

Twenty phase-interpolating voltages (V₁-V₂₀) are generated by four paths of serial resistors across the adjacent orthogonal triangular signals, and are then compared to the zero-crossing voltage (V_CM) in ultra-low-cost five-transistor comparators. The subsequent rising-edge detectors (REDs) based on a 3-ns delay cell and an AND gate, generate 20 groups of narrow pulses, which are combined together via two-stage cascaded OR gates.

Since the phase-interpolating signals are calibrated to be centered at V_CM via CMFB modules and are then discriminated to V_CM in the comparators, high PVT robustness of frequency multiplication is achieved.

Figure 5 shows the detailed timing diagram of the frequency multiplier. The input clock (F_IN) is divided-by-2 to quadrature square waves, which then are converted to orthogonal triangular waves. The following four paths of resistive phase interpolators with a phase step of 18° generate 20-phase square signals at the comparator outputs, which are then converted to 20 paths of narrow pulses by the REDs. All the pulses are finally combined to get a high-frequency clock (F_out) with a multiplication factor of 10, since there are 20 output pulses during each two input clock periods.

In this design, V_CM = 0.6 V is generated from the resistive subdivision of 1.2-V supply. The biasing currents for both comparators and square-triangular converters, are generated by a simple current mirror with the input reference current being externally provided.

4. Experimental Results

The proposed ten-fold frequency multiplier is implemented in a standard 65-nm CMOS, whose layout is shown in Figure 6, where all the submodules are clearly demonstrated. The silicon area of 0.06 mm² is observed, and the overall power consumption is 0.45mW from a 1.2-V supply.

Figure 7 shows the transient waveforms and output frequencies of the frequency multiplier, under the power supply (V_DD) fluctuation of ±10% (1.08V, 1.20V, 1.32V). Centered at 160 MHz, the output frequency has the maximum deviation of 7.5% (155MHz~172MHz), from the same 16-MHz input clock.

Figure 8 shows the output frequency components, under different process corners (TT / SS / FF) and temperature variations from -40℃ and 90℃. Located at 160 MHz, the output frequency is 160MHz has the maximum deviation of 6.3% (152MHz~170MHz).

Figure 9 shows the output spectra under the input frequencies of 12-20 MHz and the input power (P_IN) of -2.0 dBm. With the multiplication factor of 10, the output signals are located at 120 MHz / 160 MHz / 200 MHz, respectively, with a typical output power (P_OUT) of -9.80 dBm. The spurs less than -28dB are also observed, to show a good frequency stability. The frequency multiplication efficiency (η) of 9.6% is achieved and depicted in (3), under the power dissipation (P_diss) of 0.45 mW. The proposed frequency multiplicator supports a wide input frequency range of 12-20 MHz or ±25%.

$$\eta ={\displaystyle \frac{P_{OUT}}{P_{IN}+P_{diss}}}={\displaystyle \frac{0.1047mW}{0.6310mW+0.45mW}}=9.6\mathrm{\%}$$

(3)

The frequency multiplication performances are summarized and compared to the existing designs in Table 1. The proposed work has the following merits: 1) half-digital implementation with small-sized (0.06 mm²) ultra-low-dissipation (0.45 mW) features; 2) the common-mode feedback and comparison mechanism to optimize the multiplication efficiency up to 9.6% without error calibration / correction; and 3) reconfigurable multiplication factor by modifying the resistor number (k).

5. Conclusions

A small-sized five-segment triangular-resistance phase interpolation scheme is proposed and implemented in 65-nm CMOS. Under the input frequency of 12-20 MHz, the reconfigurable frequency-multiplication factor centered at 10 is achieved, with the multiplication efficiency up to 9.6% and the ultra-low power consumption of 0.45 mW from a 1.2-V supply.

The proposed frequency multiplier has the following advantages: 1) a reconfigurable multiplication factor depending on the interpolating resistor number; 2) a high-efficiency / low-cost / low-power topology with semi-digital implementation; and 3) high PVT robustness with V_CM calibration and discrimination.