Version 1
: Received: 30 April 2024 / Approved: 1 May 2024 / Online: 1 May 2024 (07:52:13 CEST)
How to cite:
Vgenopoulos, A.; Kordas, K.; Lasagni, F.; Perrella, S.; Polini, A.; Vari, R. Data Readout Techniques on FPGA for the ATLAS RPC-BIS78 Detectors. Preprints2024, 2024050049. https://doi.org/10.20944/preprints202405.0049.v1
Vgenopoulos, A.; Kordas, K.; Lasagni, F.; Perrella, S.; Polini, A.; Vari, R. Data Readout Techniques on FPGA for the ATLAS RPC-BIS78 Detectors. Preprints 2024, 2024050049. https://doi.org/10.20944/preprints202405.0049.v1
Vgenopoulos, A.; Kordas, K.; Lasagni, F.; Perrella, S.; Polini, A.; Vari, R. Data Readout Techniques on FPGA for the ATLAS RPC-BIS78 Detectors. Preprints2024, 2024050049. https://doi.org/10.20944/preprints202405.0049.v1
APA Style
Vgenopoulos, A., Kordas, K., Lasagni, F., Perrella, S., Polini, A., & Vari, R. (2024). Data Readout Techniques on FPGA for the ATLAS RPC-BIS78 Detectors. Preprints. https://doi.org/10.20944/preprints202405.0049.v1
Chicago/Turabian Style
Vgenopoulos, A., Alessandro Polini and Riccardo Vari. 2024 "Data Readout Techniques on FPGA for the ATLAS RPC-BIS78 Detectors" Preprints. https://doi.org/10.20944/preprints202405.0049.v1
Abstract
The firmware developed for the readout and trigger processing of the information emerging from BIS78-RPC Muon Spectrometer chambers in the ATLAS experiment at CERN, is presented here, together with data processing techniques, data acquisition software and tests of the readout chain system, on the road to make these chambers operational in the ATLAS experiment. This work is performed in the context of the BIS78-RPC project, which deals with the pilot deployment of a new generation of sMDT+RPC chambers in the experiment. Such chambers are planned to be fully deployed in the whole barrel inner layer of the Muon Spectrometer during the Phase-II upgrade of the ATLAS experiment. On-chamber front-ends include an amplifier, a discriminator ASIC and an LVDS transmitter. The signal is digitized by CERN HPTDC chips and then processed by an FPGA which is the heart of the readout and trigger processing, using various techniques. The work presented here is a continuation of the work presented in [1].
Keywords
CERN; ATLAS; experiment; HEP; high energy physics; readout; trigger; electronics; FPGA; xilinx; firmware; gateware; TDC; RPC; detectors; GBT
Subject
Engineering, Electrical and Electronic Engineering
Copyright:
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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