Park, J.; Lee, J.; Abraham, J.A.; Kim, B. A Tunable Foreground Self-Calibration Scheme for Split Successive-Approximation Register Analog-to-Digital Converter. Electronics2024, 13, 755.
Park, J.; Lee, J.; Abraham, J.A.; Kim, B. A Tunable Foreground Self-Calibration Scheme for Split Successive-Approximation Register Analog-to-Digital Converter. Electronics 2024, 13, 755.
Park, J.; Lee, J.; Abraham, J.A.; Kim, B. A Tunable Foreground Self-Calibration Scheme for Split Successive-Approximation Register Analog-to-Digital Converter. Electronics2024, 13, 755.
Park, J.; Lee, J.; Abraham, J.A.; Kim, B. A Tunable Foreground Self-Calibration Scheme for Split Successive-Approximation Register Analog-to-Digital Converter. Electronics 2024, 13, 755.
Abstract
The capacitor-mismatch among diverse defects caused by the manufacturing process variations significantly affects the linearity of capacitor-array used to implement the capacitive digital-to-analog converter (CDAC) in the successive-approximation-register (SAR) analog-to-digital converter (ADC). Accordingly, the linearity of the SAR ADC is limited by that of capacitor-array, resulting in serious yield loss. This paper proposes an efficient foreground self-calibration technique to enhance the linearity of the SAR ADCs by mitigating the capacitor-mismatch based on the split ADC architecture along with variable capacitors. In this work, two ADC channels (i.e., ADC1 and ADC2) for the split ADC architecture include their capacitive DACs (CDACs) whose binary-weighted capacitor-arrays consist of variable capacitors. A charge-sharing SAR ADC is used for each ADC channel. In the normal operation mode, their digital outputs are averaged to be the final ADC output, as in a conventional split ADC. In the calibration mode, every single binary-weighted capacitor for the two ADCs is sequentially calibrated by making parallel or/and antiparallel connection among two or thee capacitors from the two channels. For instance, because the capacitors of the CDACs ideally exhibit the binary-weighted relation as Cn=2×Cn−1, variable capacitor Cn of ADC1 can be updated to be closest to the sum of Cn−1 of ADC1 and Cn−1 of ADC2 for the calibration. For the process, the two capacitor-arrays of the two ADCs can be reconfigured to be connected to each other, so that Cn of ADC1 can be connected with two of Cn−1 of ADC1 and ADC2 in antiparallel. The two voltages at the top and the bottom plates of the CDAC are compared by a comparator of ADC1, and the comparison results are used to update Cn. This process is iterated, until Cn is in agreement with the sum of two of Cn−1. Finally, all the capacitors can be calibrated in this way to have the binary-weighted relation. The simulation results based on the proposed work with a split SAR ADC model verified that the proposed technique can be practically used, by showing that the total-harmonic-distortion and the signal-to-noise-and-distortion ratio were enhanced by 21.8-dB and 6.4-dB, respectively.
Keywords
self-testing; alternative testing; mixed-signal testing; manufacturing test; production test; built-in-self-test (BIST); self-calibration; self-healing; analog to digital converter (ADC)
Subject
Engineering, Electrical and Electronic Engineering
Copyright:
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
