Wang, Y.; Thangarasu, B.K.; Mahalingam, N.; Ma, K.; Meng, F.; Huang, Y.; Yeo, K.S. A Full-Duplex 60 GHz Transceiver with Digital Self-Interference Cancellation. Electronics2024, 13, 483.
Wang, Y.; Thangarasu, B.K.; Mahalingam, N.; Ma, K.; Meng, F.; Huang, Y.; Yeo, K.S. A Full-Duplex 60 GHz Transceiver with Digital Self-Interference Cancellation. Electronics 2024, 13, 483.
Wang, Y.; Thangarasu, B.K.; Mahalingam, N.; Ma, K.; Meng, F.; Huang, Y.; Yeo, K.S. A Full-Duplex 60 GHz Transceiver with Digital Self-Interference Cancellation. Electronics2024, 13, 483.
Wang, Y.; Thangarasu, B.K.; Mahalingam, N.; Ma, K.; Meng, F.; Huang, Y.; Yeo, K.S. A Full-Duplex 60 GHz Transceiver with Digital Self-Interference Cancellation. Electronics 2024, 13, 483.
Abstract
This paper presents the design and measurement of an IEEE 802.11ad standard compatible RF transceiver for 60GHz wireless communication system. In addition to the traditional half-duplex (HD) mode, this work supports full-duplex (FD) operation to deliver better channel utilization and faster response time for the system. The isolation between the transmitter and receiver from the architecture design to system integration for FD operation has been fully considered. A digital self-interference cancellation (DSIC) is implemented in MATLAB to verify the FD performance. The super-heterodyne architecture with an intermediate frequency (IF) of 12GHz is designed to suppress the image frequencies without using extra filters. A flexible phase-locked loop (PLL) synthesizer provides a local oscillator (LO) frequency with a 2kHz resolution. Other than the time division duplex (TDD) mode used in the conventional 60GHz system, a wide bandwidth baseband digital variable gain amplifier (DVGA) with a 3dB bandwidth of more than 4GHz also supports frequency division duplex (FDD) operation. The transceiver chip is fabricated in Tower Jazz 0.18µm SiGe BiCMOS process. With on-board antenna, the transceiver covers all four channels in 802.11ad standard with MCS-12 (7.04Gbps under 1.76GSym/s and 16-QAM) under 1.5m. In the proposed system design, the RF frontend based self-interference (SI) suppression from the local transmitter to receiver LNA is around 54dB. To achieve a practical FD application, the SI is further suppressed with the help of digital SI compensation. The measured power consumption for transmitter and receiver configuration is 194mW and 231mW, respectively, in HD mode and 398mW for FDD or FD operation mode.
Keywords
60GHz communication; 802.11ad; Digital Self-Interference Cancellation (DSIC); Frequency Division Duplex (FDD); Full-Duplex (FD); Low Power Consumption; Self-Interference (SI); Transceiver SoC; SiGe BiCMOS
Subject
Engineering, Electrical and Electronic Engineering
Copyright:
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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