Foundry-processed Compact and Broadband Adiabatic Optical Power Splitters with Strong Fabrication Tolerance

1. Introduction

Power splitters are among the most fundamental building blocks of complicated on-chip optical circuits. They are used in optical switches [1], modulators [2], programmable optical circuits [3], and multiplexers [4], to name a few. Ideal power splitters should have low losses, broad bandwidth, compact size, high tolerance to fabrication errors, and small deviations from the intended power splitting ratio. In addition, it is desired that the minimum feature sizes of power splitters are large (>150 nm) so that they are suitable for production at complementary metal oxide semiconductor (CMOS) foundries using mass-production. Satisfying these criteria simultaneously has proven to be challenging. There have been a wide variety of reported implementations of on-chip optical power splitters with differing strengths and weaknesses when the above-mentioned performance metrics are considered.

Among the various types of optical power splitters, directional couplers can achieve low loss and arbitrary power splitting ratios [5]. Yet, they are typically wavelength sensitive, making it difficult to realize polarization-insensitive and broadband response [6]. This problem has been partially solved by replacing the straight directional couplers with curved waveguides [1,7], which yields a broader bandwidth. The inherent strong polarization sensitivity, on the other hand, is difficult to overcome. Alternatively, power splitters based on multimode interferometers (MMIs) work using the self-imaging principle [8] and can be designed for an arbitrary number of inputs and outputs [9], as well as arbitrary splitting ratios [10]. Generally, MMI power splitters are less sensitive to wavelength than directional couplers, although the designed devices can have a large footprint. For example, as in the case of a 2×2 3 dB coupler designed to operate with the TE0 and TE1 modes, the device length of 86.5 $\mu$m has been reported [11], whereas, in the case of 1x4 and 1x8 power splitters device lengths of 36 $\mu$m and 47.8 $\mu$m were achieved, respectively [12]. More compact devices and polarization-insensitive operation have been achieved by engineering the width and thickness of the MMI power splitters, which yielded a footprint of 1.5 x 1.8 $\mu$m² [13]. However, this device was designed for a 300 nm thick Si layer, which is not commonly used by industrial foundries. More successful implementations of MMI power splitters have been achieved by modifying the profile of the MMI region, yielding in a very compact and low-loss operation [14,15]. One downside of MMI power splitters is that the profile of the device between the MMI region and the output waveguides changes abruptly. This abrupt change constitutes a source for reflections and imbalance in the output, where a slight imbalance in the output waveguides can cause imperfect splitting or increased losses, as we have demonstrated a similar effect in previous work [16].

More recently, subwavelength gratings (SWG) have been used to improve the performance of optical power splitters. For example, the bandwidths of directional coupler-based power splitters were increased via utilizing SWGs [17,18]. A variety of designs for SWG-assisted directional couplers have been reported with low losses and broad bandwidth [19,20,21,22]. SWG-assisted MMI-based power splitters have also been designed to improve the bandwidth, losses, and footprint of traditional MMI power splitters [23,24]. Moreover, SWG-assisted Y-junctions power splitters have shown good performance [25,26,27]. However, it is important to note that the above referenced works report devices with minimum feature sizes smaller than 135 nm, making them unsuitable for large-scale fabrication at CMOS foundries.

In addition to the aforementioned approaches, various inverse design algorithms have been used to optimize the device power splitting efficiencies, where the device is divided into pixels [28,29,30,31] or subwavelength-sized stripes [32]. However, these optimization approaches yield devices that only work with the TE mode and consist of many small-sized features, which can result in fabrication intolerance [33]. When these devices are designed with considerations of foundry limitations, inverse-designed power splitters with minimum feature sizes as large as 200 nm can be achieved [34]. However, these devices suffer from high losses and large output variations. Topological photonic devices have been an alternative to inverse-designed photonic components with small features [35]. With topological optimizations, foundry-compliant designs can be achieved by putting heavy constraints on the design [36,37]. In addition, machine learning models have been used to correct photonic device design layouts prior to fabrication [38]. Yet, these devices typically suffer from over 0.5 dB losses and there is little discussion in the literature on making them polarization insensitive.

Unlike other power splitter implementations, adiabatic optical power splitters are inherently low-loss, broadband, tolerant to fabrication error, and polarization-insensitive. These advantages can be realized even with devices with large minimum feature sizes, yet the resultant adiabatic components are typically much longer than their counterparts. The long device lengths ensure that the mode evolution is slow enough to avoid radiation losses. Using small minimum feature sizes could reduce the device length, which has been demonstrated in the case of a 1×2 adiabatic power splitter with a 30 nm minimum feature size, resulting in a coupling length of 5 $\mu$m [39].Unfortunately, such small features are well beyond fabrication limitations set by foundries. The majority of the adiabatic power splitters with larger minimum feature sizes have linear taper profiles [40,41,42,43,44,45,46]; whereas the linear taper profiles are not ideal for adiabatic transitions and using non-linear profiles can significantly reduce the device lengths even with large minimum feature sizes.

Methods such as shortcuts to adiabaticity [47,48] and quasi-adiabatic dynamics [49,50,51] have been used to design adiabatic taper profiles that resulted in 2×2 3 dB couplers with much shorter lengths as compared to the devices with linear taper profiles. Reference [51] demonstrates over an order-of-magnitude reduction in the length of a 2×2 3 dB coupler as compared to a 3 dB coupler with a linear taper profile, where a 11.7 $\mu$m device length and a 3±0.5 dB bandwidth of 75 nm were achieved. Other methods for designing adiabatic power splitters include ensuring that the adiabatic transition losses are maintained below a certain level by engineering the rate of change of the taper width profile [52]. In Ref. [53], we have developed a different approach where the width profiles of the adiabatic tapers were expressed in terms of a polynomial function and the coefficients of the polynomial terms were optimized using numerical methods for the lowest losses for a given taper length. This method has the advantage of providing more design flexibility for the taper. Using this approach, we have shown a reduction by half in the length of an adiabatic fiber-to-chip light coupler with no additional losses. More recently, we have also applied this technique to a 1×2 Y-junction power splitter with a 120 nm minimum feature size and have shown less than 0.25 dB and 0.23 dB losses for the TE and TM modes, respectively, in the spectral range of 1500 nm and 1600 nm [54]. The polynomial taper optimization is yet to be applied for the design of adiabatic power splitters with large minimum feature sizes and the performance of these devices are to be analyzed when a CMOS-compatible fabrication process is used.

In this work, we propose and implement a polynomial-based adiabatic taper profile optimization algorithm for the design of 1×2 and 2×2 adiabatic optical power splitters. The designed 1×2 Y-Junction power splitters yielded coupling lengths ranging from 10 $\mu$m to 30 $\mu$m for minimum feature sizes ranging from 140 nm to 200 nm. The experimental results show that a device with 180 nm minimum feature size can have a coupling length of 20 $\mu$m with losses lower than 0.5 dB for both the TE and TM modes between 1480 nm and 1585 nm. Besides, the 1×2 Y-Junction architecture can be modified to allow arbitrary power splitting ratios by tuning the gap between the coupling waveguides. We have designed power splitters with ratios of 50:50, 58:42, 68:32, 77:23, and 89:11. The measured standard deviations in the power splitting ratios for these 1×2 Y-Junction splitters were between two to six percent. In addition, a broadband 2×2 3 dB power splitter with a 16 $\mu$m coupling region was measured to have 0.7 dB losses and a bandwidth of over 130 nm, where a larger bandwidth measurement was not possible due to the range of our tunable laser source. Our experiments were performed over 9 different chips and results indicate excellent consistency of performance and significantly fabrication-tolerant power splitters.

2. 1×2 Y-Junction Optical Power Splitters

In this section, we apply our polynomial-based taper profile optimization algorithm to the design of adiabatic 1×2 Y-Junction power splitters for symmetric power splitting (50:50) and arbitrary ratio power splitting. The optimization algorithm and the design procedure are defined, followed by the experimental results.

2.1. Design Methodology for 1×2 Y-Junction Power Splitters

A schematic of the 1×2 Y-Junction power splitters is shown in Figure 1(a). The width of the tips is denoted by w_tip, and the gaps are denoted by w_gap,1 and w_gap,2. The first stage of the Y-Junction splitter is an adiabatically tapered region that gradually splits the input power from the middle waveguide to the upper and lower waveguides. The middle waveguide varies from 500 nm to w_tip, while the upper and lower waveguides vary from w_tip to 500 nm over the taper length (L_Y). The value of w_tip is the smallest feature in this design. A smaller w_tip results in shorter devices but it is typically limited by the minimum feature that is allowed by the foundry. The values of w_gap,1 and w_gap,2 are the widths of the lower and uppers gaps, respectively, and they are always chosen to be at least 20 nm wider than w_tip to reduce potential reflections due to the abrupt changes at the two ends of the tapers. After the adiabatic coupling region, the waveguides are separated by 4 $\mu$m with by using two 15 $\mu$m-long S-bends, whose length was chosen generously to ensure the losses are predominantly due to the coupling region.

When w_gap,1 and w_gap,2 are equal, the Y-Junction power splitter has a 50:50 splitting ratio. An imbalance between w_gap,1 and w_gap,2 cause the splitting ratio to vary. Here, we design 4 devices with 50:50 splitting ratios with minimum feature sizes (i.e., w_tip) of 140 nm, 160 nm, 180 nm, and 200 nm. Designs with different w_tip allow us to observe the effect of minimum feature size on the performance of the Y-Junction power splitters. For these devices w_gap,1 and w_gap,2 are equal and they are 20 nm wider than w_tip. To realize Y-Junctions with arbitrary splitting ratios, we keep w_tip and w_gap,1 fixed at 180 nm and 200 nm, respectively, and vary w_gap,2 depending on the power splitting ratio we wish to achieve.

The width of the upper and lower tapers is defined by a polynomial function with 8 terms, given by

$$w^{up}\left(z_{norm}\right)={\phantom{\sum }}_{}{\sum }_{n=1}^8{c}_n{z}_{norm}^{p_n},$$

(1)

where p_n is the power of the n^th term, and c_n is the coefficient of the n^th term. The chosen p values are [0, 0.3, 0.5, 0.7, 1, 2, 5, 10], and c_n values are to be determined by the optimization. The normalized length (z_norm) is defined as z_norm=z/L_Y, and is limited by the bounds of [0,1]. Using the polynomial function in Eq. 1 allows great freedom in modifying the shape of the taper. To satisfy the boundary conditions (i.e, $w^{up}\left(0\right)$=w_tip, and $w^{up}\left(1\right)$=500 nm), we ensure that

$$c_1=w_{tip}\&p_1=0\&{\phantom{\sum }}_{}{\sum }_{n=1}^8{c}_n=500\mathrm{nm}.$$

(2)

We define the width of the middle taper in terms of the widths of the upper and lower tapers (i.e., $w^{up}$),

$$w^{mid}\left(z_{norm}\right)=500\mathrm{nm}-(500\mathrm{nm}-w_{tip}).{\left(\frac{w^{up}\left(z_{norm}\right)-w_{tip}}{500\mathrm{nm}-w_{tip}}\right)}^{\alpha },$$

(3)

where $\alpha$ is a parameter that determines the relation between the widths of the upper and middle tapers. $\alpha$ serves as a value that provides an additional degree of freedom in the design and causes the profile of the middle taper to vary differently from the profiles of the upper and lower tapers.

The Y-Junction power splitters were modeled with Lumerical Eigenmode Expansion (EME) solver. With the EME method, the 3-D device is divided into 2-D slices, where the finite-difference method is used to calculate eigenmodes at each slice. Once the eigenmodes are calculated, mode evolution can be calculated along the taper with great accuracy. A significant advantage of the EME method is that the distance between the cells can be modified after the calculation of eigenmodes to generate the desired taper profiles without the need for recalculating the eigenmodes. The p_n values are chosen prior to the optimization, and the taper profiles are optimized by optimizing the c_n values. A wide range of p values were chosen to allow for a wide range of taper shapes. Small p values (p<1) allow for rapid change of shape at the beginning of the taper, followed by a more gradual change towards the end of the taper while larger p values (p>1) cause the taper shape to vary slowly, followed by a rapid change of width. The c_n values determine to what degree these shapes should be included in the optimized structure. A particle swarm optimization algorithm was used to optimize the c_n values. The optimization goal was set to minimize the taper losses at the wavelength of 1550 nm for the TE, or the TM mode, whichever is higher. The number of particles was selected to be 45 and the optimization was run for 25 generations, or until the result has not improved for 3 consecutive generations, whichever happens first. After the optimization, we simulated the devices with the 3-D finite-difference time-domain (FDTD) method to ensure the accuracy of the results. The field profiles along an optimized 1×2 50:50 Y-Junction power splitter for a minimum feature size of 180 nm (i.e., w_tip=180 nm, w_gap,1=w_gap,2=200 nm) are shown for the TE and TM modes in Figure 1(b), and (c), respectively.

2.2. Profile-optimized 1×2 Y-Junction Power Splitters

To understand the effect of the $\alpha$ parameter on the taper losses, we optimized a 50:50 Y-Junction power splitter with a 180 nm minimum feature size for $\alpha$ values ranging from 0.2 to 1. The simulated taper losses for the TE mode, as a function of the Y-Junction length, are presented in Figure 2(a). For all the $\alpha$ values we analyze here, the required Y-Junction lengths are drastically shorter than a linear Y-Junction, which is shown with the dashed lines. We note that for the $\alpha$ value of 0.5 and lower, the taper losses are minimized rapidly. Moreover, we observed that the $\alpha$ value of 0.5 works well for all other minimum feature sizes and hence we continue our optimizations by setting $\alpha$ equal to 0.5.

Figure 2(b) and (c) show the minimized taper losses for the TE and TM modes, respectively, at a wavelength of 1550 nm and for an $\alpha$ parameter of 0.5. For both the TE and TM modes, devices with smaller minimum feature sizes tend to require shorter Y-Junction lengths to achieve low losses (<∼0.05 dB). To ensure that the taper losses are minimal for both modes, we choose coupling lengths of 10 $\mu$m, 15 $\mu$m, 20 $\mu$m, and 30 $\mu$m for the minimum feature sizes of 140 nm, 160 nm, 180 nm, and 200 nm, respectively.

The excess losses for the optimized devices were simulated with the FDTD method and are shown in Figure 2(d) for the four minimum feature sizes. For the TE mode, all minimum feature sizes achieve very low excess losses around 1550 nm, as expected from the losses calculated with the EME solver. However, at shorter wavelengths, the excess losses increase, which is more pronounced for the TE mode and for larger minimum feature sizes. This is because at shorter wavelengths, the TE mode is more strongly confined in the Si core, hence, the Y-Junction length needs to be longer as compared to longer wavelengths for low-loss power splitting. Yet, the excess losses for the TE mode are lower than 0.2 dB for wavelengths longer than 1500 nm. For the TM mode, on the other hand, the excess losses are much less wavelength dependent and are between 0.15 dB and 0.25 dB in the whole spectrum range. These values are slightly above the taper losses estimated by the EME calculations. Further analysis showed that the abrupt changes at the beginning and end of the tapers cause an extra ∼0.1 dB loss, which was not included in the EME analysis.

To design 1×2 Y-Junctions with arbitrary power splitting ratios, we choose a minimum feature size of 180 nm and keep w_tip and w_gap,1 fixed at 180 nm and 200 nm, respectively, while varying w_gap,2. For each value of the w_gap,2, we optimize the profile of the device to minimize the taper losses for the TE mode. Although arbitrary splitting ratios are achievable for both modes, for a given w_gap,2 value, Y-Junctions will have different splitting ratios for the TE and TM modes. To prove the effectiveness of this structure, we design our devices for the TE mode only, although the same optimization can be done for the TM mode. The ratio of the transmitted power to the lower arm of the Y-Junction power splitter is shown in Figure 3(a) for the TE mode as a function w_gap,2. Power splitting ratios from 50:50 to 98:2 can be achieved by varying the w_gap,2 from 200 nm to 520 nm.

We chose values for w_gap,2 of 200 nm, 220 nm, 250 nm, 290 nm, and 355 nm, which result in power splitting ratios of 50:50, 58:42, 68:32, 77:23, and 89:11, respectively. The spectra of the power ratios at the lower arm are shown in Figure 3(b). The spectral variations in the splitting ratios are within ±1% for all the Y-Junction power splitters throughout the wavelength range of 1450 nm to 1650 nm. The excess losses for these devices are shown in Figure 3(c), where the excess losses are below 0.2 dB for wavelengths longer than 1500 nm. The electric field profiles (|E|) along the Y-Junction splitters show that the power splitting takes places with little radiation losses at 1550 nm wavelength for w_gap,2 of 250 nm and 355, as shown in Figure 3(d) and (e), respectively.

2.3. Experimental Results for 1×2 Y-Junction Power Splitters

The 1×2 Y-Junction power splitters were fabricated at the Advanced Micro Foundry (AMF), in Singapore, on a 220 nm SOI platform with a 3 $\mu$m buried oxide layer. The devices were then coated with a 2.3 $\mu$m thick SiO₂ cladding layer. The edges of the chips were deep etched to allow access to the edge couplers. Scanning electron microscope images of the resultant Y-Junctions with 50:50 and 89:11 power splitting ratios are shown in Figure 4(a) and (b), respectively, for a minimum feature size of 180 nm.

To measure the excess losses, light from a tunable laser was passed through a waveplate and a linear polarizer to control the polarization of the light. Ten percent of the light was then sampled using a fiber-based power splitter in order to measure the power of the light before the chip. The rest of the light was coupled into the chip. Light coupling into and out of the chip was performed with polarization maintaining lensed-fibers with a 5 $\mu$m spot size. The lensed-fiber at the output was connected to a fiber-based polarization beam splitter, to ensure the measured output power belongs to either the TE or the TM mode, and any depolarization that might have occurred in the chip or in the fibers was not measured. The transmission was obtained from the ratio of the output power to the sampled input power and was normalized with a reference measurement, whose path consisted of two edge couplers and a waveguide connecting the edge couplers. Transmission through Y-Junction power splitters were then measured, and the excess losses were calculated after measuring the transmission through both arms of the devices. The excess losses were measured on 9 different chips, and the results were averaged, and standard deviations were calculated. The standard deviation in the transmission due to the variations of losses of edge couplers and waveguides were measured to be 0.1 dB for the TE mode, and 0.2 dB for the TM mode for the same chip, with nearly no wavelength sensitivity. For measurements involving Mach Zehnder interferometers (MZIs), we used a broadband superluminescent diode source centered at 1550 nm with a 3 dB bandwidth of 50 nm and measured the output power with an optical spectrum analyzer. The MZI spectra were then used to deduce the extinction ratios of the peaks and dips, which is used as a metric for how equally a 50:50 splitter splits the optical power. A good extinction ratio is typically over 20 dB, which ensures that the power splitting ratio is confined within 50±5%.

The average measured excess losses for the 50:50 Y-Junction power splitters are shown in Figure 5(a) (TE) and Figure 5(b) (TM) for the four different minimum feature sizes. The Y-Junction power splitters with 140 nm and 160 nm minimum feature sizes perform poorly, as it is evident from excess losses higher than 1 dB. The devices with larger minimum feature sizes (i.e., 180 nm and 200 nm), on the other hand, show drastically lower losses. Although features as small as 140 nm are allowed by the foundry, the significant minimum feature size dependency shows that the fabrication process is better suited for devices with larger features. Among the four minimum feature sizes, the 180 nm minimum feature size set has losses lower than 0.4 dB for both the TE and TM modes in the wavelength range of 1490 nm and 1590 nm.

Figure 5(c) and (d) show the average excess losses for the TE and TM modes, respectively, for a minimum feature size of 180 nm. The shaded regions show one standard deviation above and below the average excess losses, calculated from our measurements on nine chips. The standard deviation for the TE and TM modes are relatively constant around 0.2 and 0.3 dB, respectively, throughout the spectrum. These values are comparable to the deviations among different edge couplers on the same chip, which are 0.1 dB and 0.2 dB for the TE and TM modes, respectively. Yet, it is important to note that the standard deviations Figure 5(c) and (d) are a combination of deviations in light coupling losses, waveguide losses, and the losses of the Y-Junction power splitters.

To analyze the balance in power splitting, an MZI with a length imbalance of 204 $\mu$m was constructed with two Y-Junction power splitters. Representative MZI transmission spectra are shown in Figure 5(e) and (f) for the TE and TM modes, respectively, for the 180 nm minimum feature sizes. The extinction ratios between the peaks and the dips are over 20 dB for the wavelength range of 1460 nm to 1610 nm for both modes. When the average of the extinction ratios is concerned, the 180 nm minimum feature size outperforms the other minimum feature sizes, as shown in Figure 5(g) and (h). The average extinction ratios are over 24 dB between 1480 nm and 1590 nm for both modes for the 180 nm minimum feature size. Although Y-Junctions with 160 nm and 200 nm minimum feature sizes have 20 dB extinction ratios over a broadband for both modes, the Y-Junction with 140 nm minimum feature size performs poorly with an extinction ratio under 20 dB for the TE mode. It is worthwhile to note that we were unable to extract the extinction ratios from some of the MZI spectra for Y-Junctions with 140 nm and 160 nm minimum feature sizes due to low extinction ratios or noisy spectrum. Hence, the extinction ratios for devices with 140 nm and 160 nm minimum feature sizes in Figure 5(g) and (h) were averaged over four and five spectra, respectively. For the devices with 180 nm and 200 nm minimum feature sizes, the average extinction ratios were calculated from all nine devices we tested. We have previously observed a similar minimum feature size dependency of splitting ratios, where devices with moderate minimum feature sizes performed better in terms of loss and splitting ratio than devices with small and large minimum feature sizes [55].

The average excess losses for the TE mode of the arbitrary ratio power splitters are shown in Figure 6(a) for varying w_gap,2. All the devices we have analyzed here have excess losses lower than 0.6 dB for wavelengths longer than 1490 nm, indicating that the varying of the splitting ratio does not affect the bandwidth significantly. Figure 6(b) shows the spectra of the average power ratio at the lower arm of the Y-Junction power splitter along with the simulated results shown as dashed lines. For the power splitters with designed splitting ratios of 50:50, and 58:42, the experimental results are in excellent agreement with the simulated splitting ratios. For the splitters with designed splitting ratios of 68:32, 77:23, and 89:11, however, the differences are 3%, 7%, and 5%, respectively, in the C-band. This discrepancy might have been caused by the gaps between the waveguides being affected disproportionately by the fabrication errors. Such fabrication errors typically do not affect the results for splitting ratios close to 50:50, thanks to the inherent fabrication tolerance of the adiabatic power splitters, but they are more pronounced when the asymmetry in the structure is higher.

The standard deviations in the splitting ratios on different chips are shown in Figure 6(c) for the varying w_gap,2 values. The standard deviations range between 2% and 4% with the exception of a w_gap,2 of 290 nm, where the deviation is around 6%.

3. Broadband 2×2 50:50 Optical Power Splitters on 90 nm Slab

In this section, we present our 2×2 50:50 optical power splitters fabricated on a 90 nm Si slab along with the taper profile optimization. We discuss the design procedure, experimental excess losses, and splitting ratios of the devices.

3.1. Design of 2×2 50:50 Power Splitters

A schematic of the 2×2 50:50 power splitter is shown in Figure 7(a). The device architecture has been borrowed from Ref. [46]. This power splitter is designed on a 90 nm Si slab, which is a commonly offered thickness by foundries. For the TE mode, the device shows a significant reduction in the coupling length as compared to a device with linear coupling region. However, the 2×2 50:50 power splitters can also be designed (and optimized) without the 90 nm slab, and hence can be made to operate with both the TE and TM mode.

The use of a 90 nm Si slab requires conversion from the bus-waveguide to rib-waveguide modes. Prior to the conversion, the upper input waveguide was tapered down to 400 nm, while the lower input waveguide was tapered up to 600 nm, over a 1 $\mu$m long taper. Then, 3 $\mu$m long profile-optimized tapers on the 90 nm slab were used, while the widths of the 220 nm Si ribs remained constant. This taper was followed by 25 $\mu$m long Bezier bends that bring the gap between the waveguides from 4 $\mu$m down to 200 nm. Long bends are needed to ensure low losses, since rib-waveguides are typically lossy when sharp bends are used. Furthermore, when the waveguides get closer, coupling between waveguide modes become stronger, hence bends need to have a larger radius as the bends get closer to each other.

In the adiabatic coupling stage, the upper and lower waveguides are tapered from 400 nm and 600 nm, respectively, to a width of 500 nm. The mode on the upper arm is transformed into the anti-symmetric waveguide mode at the output of the adiabatic coupling stage, while the mode in the lower arm is transformed into the symmetric mode, whose profiles are shown in Figure 7(a). The width of the upper waveguide is given by

$$w^{up}\left(z_{norm}\right)={\phantom{\sum }}_{}{\sum }_{n=1}^8{c}_n{z}_{norm}^{p_n}.$$

(4)

The selected p_n values are [0, 0.1, 0.3, 0.5, 0.7, 1, 3, 5]. The selected p_n values are smaller than the ones for the 1×2 Y-Junction power splitter. This is because the 2×2 50:50 power splitters perform better with smaller p values and including 0.1 in the p values has reduced the times to find the optimal structures. To satisfy the boundary conditions (i.e., w^up(0)=400 nm, and w^up(1)=500 nm), we ensure that

$$c_1=400\mathrm{nm}\&p_1=0\&{\phantom{\sum }}_{}{\sum }_{n=1}^8{c}_n=500\mathrm{nm}.$$

(5)

We define the width of the lower waveguide in terms of the width of the upper waveguide according to

$$w^{down}\left(z_{norm}\right)=600\mathrm{nm}-(600\mathrm{nm}-500\mathrm{nm}).{\left(\frac{w^{up}\left(z_{norm}\right)-500\mathrm{nm}}{600\mathrm{nm}-500\mathrm{nm}}\right)}^{\alpha },$$

(6)

where $\alpha$ is a parameter, similar to the one used in the optimization of the 1×2 Y-Junction power splitter. Since two TE mode evolutions take place in the adiabatic coupling stage, we minimize whichever transition has higher losses. The adiabatic coupler stage is followed by 11 $\mu$m long Bezier bends, and a rib-waveguide to bus waveguide converter with a length of 2 $\mu$m.

Figure 7(b) shows the optimized taper losses as a function of the coupler length (L_c), along with the linear taper (red solid line) for comparison. The linear taper requires approximately 60 $\mu$m coupling length to achieve losses lower than 0.1 dB. On the other hand, profile optimized tapers can achieve 0.1 dB losses with a coupling length of approximately 12 $\mu$m and 16 $\mu$m, depending on the $\alpha$ parameter. Among the $\alpha$ parameters analyzed here, an $\alpha$ of 0.3 achieved the lowest losses with the shortest length; hence, we have used an $\alpha$ parameter of 0.3 and coupling length of 16 $\mu$m. When the coupling region is simulated with the 3-D FDTD method, an excess loss of less than 0.2 dB can be achieved over a bandwidth of 200 nm, as shown in Figure 7(c). Moreover, the excess loss difference between the 2 inputs is less than 0.05 dB throughout the spectrum, indicating a balance in losses seen from both inputs. Figure 7(d) and (e) show the field profiles of the mode evolution from the inputs to the anti-symmetric and symmetric modes, respectively. The mode profiles show successful transition from inputs to the desired output modes.

3.2. Experimental Design for the 2×2 50:50 Power Splitters

A scanning electron microscope image of the 2×2 50:50 power splitter is shown in Figure 8(a). Testing for the 2×2 50:50 power splitters was done similar to that of the 1×2 Y-Junction power splitters. The transmission through the 2×2 50:50 power splitters were measured from both inputs to both outputs; hence, there are four measurements for a single device, whereas two measurements were taken for the 1×2 Y-Junction power splitters. The excess losses were obtained for each input. The average excess losses of the 2×2 50:50 power splitter are shown in Figure 8(b) and (c) when input power was launched from input 1 and input 2 of the device, respectively. The excess losses fluctuate around 0.7 dB, with a standard deviation of approximately ±0.3 dB. The excess losses demonstrate excellent wavelength insensitivity in the 1460 nm to 1590 nm wavelength range. The standard deviations for the 2×2 50:50 power splitter are higher when compared to the 1×2 Y-Junction power splitter. This could be because the 2×2 50:50 power splitter has more stages, which causes more overall deviations. The mode conversion losses from the 500 nm wide Si bus waveguide to the waveguide with 90 nm slab make up some of the excess losses and deviations in loss. Lower excess losses could be achieved if this power splitter is used along with other devices that are already on a slab, such as programmable optical meshes [3].

Transmission through MZIs, consisting of two devices connected in series with a length imbalance of 160 $160\mu$m, were measured from both inputs and both outputs, totaling to four measurements per interferometer – unlike the 1×2 Y-Junction power splitters, which required only one measurement per interferometer. For this measurement, one of the 2×2 50:50 power splitters was rotated by 180 along the z-axis before creating the interferometer, so that if there is an imbalance in power splitting, it would be emphasized in the output. A representative transmission spectrum of an MZI is shown in Figure 8(d). In the wavelength range of 1450 nm to 1610 nm, extinction ratios when light power is launched from both inputs are above 20 dB. The average extinction ratios, as seen in Figure 8(e) and (f) when the light is launched from the input 1 and input 2, respectively, indicate extinction ratios greater than 20 dB in the 1460 nm and 1595 nm. Hence, the designed power splitter has an excellent balance in the splitting ratio over a wide bandwidth. We have summarized the key performance metrics for the select devices in Table 1. The data shown in Figure 8(d-f) were taken from output 1 of the device, since the extinction ratios were observed to be nearly identical regardless of which output the light was collected from.

4. Conclusions

In conclusion, we have developed an adiabatic taper profile optimization algorithm for the design of 1×2 and 2×2 power splitters with low losses, broad bandwidth, balanced splitting ratios, and compact sizes. The 1×2 Y-junction power splitters with a 180 nm minimum feature size and 20 $\mu$m coupling length showed average excess losses lower than 0.5 dB for both modes in the wavelength range of 1480 nm to 1585 nm. When the 1×2 Y-Junction power splitter geometry was modified to achieve arbitrary splitting ratios, the excess losses were maintained below 0.6 dB across the same wave-length range, while achieving splitting ratios ranging from 50% to 94% with standard deviations ranging between 2% and 6%. Similarly, 2×2 50:50 power splitters with a 16 $\mu$m coupling length were observed to have an average excess loss of 0.7 dB. Our device designs demonstrate excellent consistency across multiple chips, while ensuring low losses and wide bandwidth. With the aforementioned power splitters, we have demonstrated the effectiveness of a polynomial-based optimization algorithm for minimization of the losses of adiabatic power splitters, which results in low-loss and highly fabrication-tolerant devices with significantly improved footprints, as compared to their adiabatic counterparts. This optimization is applicable to many other adiabatic components and can accommodate devices with a wide range of minimum feature sizes.