Hong, E.; Choi, K.-A.; Joo, J. Efficient Two-Stage Max-Pooling Engines for an FPGA-Based Convolutional Neural Network. Electronics2023, 12, 4043.
Hong, E.; Choi, K.-A.; Joo, J. Efficient Two-Stage Max-Pooling Engines for an FPGA-Based Convolutional Neural Network. Electronics 2023, 12, 4043.
Hong, E.; Choi, K.-A.; Joo, J. Efficient Two-Stage Max-Pooling Engines for an FPGA-Based Convolutional Neural Network. Electronics2023, 12, 4043.
Hong, E.; Choi, K.-A.; Joo, J. Efficient Two-Stage Max-Pooling Engines for an FPGA-Based Convolutional Neural Network. Electronics 2023, 12, 4043.
Abstract
This paper proposes two max-pooling engines, named the RTB-MAXP engine and the CMB-MAXP engine, with a scalable window size parameter for FPGA-based convolutional neural network (CNN) implementation. The max-pooling operation for the CNN can be decomposed into two stages, i.e., a horizontal axis max-pooling operation and a vertical axis max-pooling operation. These two one-dimensional max-pooling operations are performed by tracking the rank of the values within the window in the RTB-MAXP engine and cascading the maximum operations of the values in CMB-MAXP engine. Both the RBM-MAXP engine and the CMB-MAXP engine were implemented using VHSIC Hardware Description Language (VHDL) and verified by simulations. They have been employed for and tested in our CNN accelerator targeting at the CNN model YOLOv4-CSP-S-Leaky for object detection.
Keywords
max-pooling; convolutional neural network (CNN); FPGA; rank tracking based max-pooling (RTB-MAXP); cascaded maximum based max-pooling (CMB-MAXP)
Subject
Engineering, Electrical and Electronic Engineering
Copyright:
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
