Banchelli, F.; Garcia-Gasulla, M.; Mantovani, F. Top-Down Models across CPU Architectures: Applicability and Comparison in a High-Performance Computing Environment. Information2023, 14, 554.
Banchelli, F.; Garcia-Gasulla, M.; Mantovani, F. Top-Down Models across CPU Architectures: Applicability and Comparison in a High-Performance Computing Environment. Information 2023, 14, 554.
Banchelli, F.; Garcia-Gasulla, M.; Mantovani, F. Top-Down Models across CPU Architectures: Applicability and Comparison in a High-Performance Computing Environment. Information2023, 14, 554.
Banchelli, F.; Garcia-Gasulla, M.; Mantovani, F. Top-Down Models across CPU Architectures: Applicability and Comparison in a High-Performance Computing Environment. Information 2023, 14, 554.
Abstract
Top-down models are defined by hardware architects to provide information on the utilization of the different hardware components. The target is to isolate the users from the complexity of the hardware architecture while giving them insight into how efficiently the code is using the resources. In this paper, we explore the applicability of 4 top-down models defined for different hardware architectures powering state-of-the-art HPC clusters (Intel Skylake, Fujitsu A64FX, IBM Power9, and Huawei Kunpeng 920) and propose a model for AMD Zen 2. We study a parallel CFD code used for scientific production to compare these 5 Top-Down models. We evaluate the level of insight achieved, the clarity of the information, the ease of use, and the conclusions that each one allows us to reach.
Keywords
Performance models; Top-Down model; HPC applications; MareNostrum 4; A64FX; Power 9; Zen 2
Subject
Computer Science and Mathematics, Hardware and Architecture
Copyright:
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
