Lauritano, M.; Baumgartner, P.; Ulusoy, A.Ç. Test Structures for the Characterization of the Gate Resistance in 16 nm FinFET RF Transistors. Electronics2023, 12, 3011.
Lauritano, M.; Baumgartner, P.; Ulusoy, A.Ç. Test Structures for the Characterization of the Gate Resistance in 16 nm FinFET RF Transistors. Electronics 2023, 12, 3011.
Lauritano, M.; Baumgartner, P.; Ulusoy, A.Ç. Test Structures for the Characterization of the Gate Resistance in 16 nm FinFET RF Transistors. Electronics2023, 12, 3011.
Lauritano, M.; Baumgartner, P.; Ulusoy, A.Ç. Test Structures for the Characterization of the Gate Resistance in 16 nm FinFET RF Transistors. Electronics 2023, 12, 3011.
Abstract
The gate resistance is a parasitic element in transistors for RF and millimeter-wave circuits that can negatively impact power gain and noise figure. To develop accurate device models, a reliable measurement methodology is crucial. This article reviews the standard measurement methodology used in the literature and proposes also an additional method, which is evaluated using suitable test structures in a 16nm FinFET process. The advantages and disadvantages of the two approaches are discussed along with their respective application scenarios
Engineering, Electrical and Electronic Engineering
Copyright:
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
