Low-Noise Amplifier and Neurostimulator in submicron CMOS for Closed-Loop Deep-Brain Stimulation (CLDBS)

1. Introduction

Deep Brain Stimulation (DBS) is a surgical procedure that involves the implantation of a medical device called a neurostimulator (often called a brain pacemaker) that sends mild impulses to specific areas of the brain through implanted electrodes [1,2,3]. The electrical current used is very low in the range of μA and is injected into strategic points in the brain, which are mostly located deep within the brain tissue. This type of procedure involves inserting implantable tips, with electrodes rings at the ends, into specific points in the thalamus, subthalamic region, globus pallidus, among others. The electrodes are then connected to the neurostimulator itself by means of extension cables containing metallic wires [4]. The neurostimulator is a device with dimensions no larger than a matchbox and includes an attached battery to provide power and be able to operate [5,6,7].

The first current use of the DBS technique dates back to 1997, when authorization was granted by the American FDA (Food and Drug Administration) for the treatment of Parkinson's disease [8]. Since then, and thanks to proven success, DBS has become first-line therapy option for relieving symptoms associated with neurological and movement disorders that are unresposible to other therapies [9], namely chronic pain [10,11], Parkinson's disease [12,13], tremor [14,15], dystonia [16,17], morbid obesity [18], Tourette's syndrome [19], essential tremor [20], and obsessive-compulsive disorder [21].

There are two paradigms for classifying DBS, namely open-loop DBS (also known as conventional DBS) and closed-loop DBS (also known as adaptive DBS or CLDBS) [22]. In the case of open-loop DBS, a neurologist manually adjusts the stimulation parameters every 3-12 months after implantation. On the other hand, in the case of closed-loop DBS, programming of stimulation parameters is performed automatically based on some measured biomarkers [22]. Biomarkers are acquired signals and they can have different natures, namely bioelectrical, psychological, biochemical, among others [22]. Biomarkers are essential indicators in closed-loop DBS because, based on the disease to be treated, they help to adaptively reconfigure the signals used in neurostimulation [22].

It is interesting to note that advances in the microelectronics are paving the way for the simultaneous acquisition of several types of biopotentials with the same microdevice resulting in the closed loop DBS. It was precisely this that motivated the development of the CMOS microdevice presented in this paper. Figure 1 illustrates the block diagram containing the acquisition, neurostimulator and control modules of a CMOS microdevice for application on CLDBS. The Low-Noise Amplifier (LNA) and the Neurostimulator modules presented in this paper are shown in yellow and green colors in the block diagram, respectively.

2. Design

The signals at the input of an LNA present a variety of challenges, such as low amplitudes, on the order of microvolts, low frequencies, very close to 0 Hz, or both. The amplifiers for neural recordings found in the literature typically exibit a mid-band gain of 40 dB, with bandwidths ranging from sub-Hz to a few kHz or even a few dozens of kHz [23,24,25,26,27,28,29,30,31,32].

Figure 2a shows the schematic of the LNA presented in this paper [32]. This amplifier is composed by an operational amplifier (OpAmp), two pairs of capacitors C₁ and C₂, and a pair of resistors R₂. The internal schematic of the OpAmp, in turn, is presented in Figure 2b. The OpAmp has a basic configuration with two stages and comprises six PMOS and four NMOS transistors. The PMOS transistors M₁ and M₂ form a differential pair, working as the input stage. The NMOS transistors M₃ and M₄ form an active pair load. The PMOS transistors M₅ and M₇ form the biasing circuit for the input and output stages, respectively. These two PMOS mirror the current I_sd9 of M₉, multiplying it to form I_sd5 and I_sd7. The NMOS M₆ forms a common source amplifier and provides additional gain to the input stage, thereby increasing the total gain of the OpAmp. The PMOS M_8p and the NMOS M_8n act as a resistance in series with the capacitor C_C, creating a dominant pole f_p and ensuring that the OpAmp is unconditional stable.

The calculation of the LNA gain requires the knowledge of the input and feedback impedances Z₁ and Z₂, respectively. These impedances are given by:

(1)

(2)

The relation of the impedances Z₁ with (Z₁+Z₂), named feedback factor, is given by:

(3)

The gain of the LNA can be easily deduced if we consider V_IM= -V_IP = V_in/2 (Figure 2) Since the complete LNA forms a difference amplifier, the voltage V_out at the output of LNA, is given by:

(4a)

(4b)

(4b)

where A(s) is the transfer function of the OpAmp. Therefore, the gain of the LNA, i.e., the feedback gain, A_f(s) is given by:

(5)

Normally, A(s) can be expressed with a single pole, or at least with a dominant pole close to the origin. However, additional poles must be considered if they exists and are located near the pass-band of the LNA. The one-pole appoximation is a useful and general model, employed here for deducing the feedback gain and to understanding the frequency behavior of the LNA. Taking the example of the existence of only one pole, the OpAmp transfer function A(s) is given by:

(6)

Now, by substituting A(s) into equation (5), a new expression for the LNA is found:

(7)

It must be noted that the transfer function of the LNA has a zero at 0 Hz and two negative poles, which are called p_L = -1/(2πf_L) and p_H = -1/(2πf_H) (f_L and f_H are postive real numbers). If A₀ is such that A₀ >> 1, then, 2πf_pA₀ >> 1/(R₂C₂), i.e., the gain × bandwidth product (GBW) of the OpAmp is such that GBW>>1/(R₂C₂), the expression for A_f(s) can be approximated as:

(8)

Additionaly, if the two poles p_L and p_H are well spaced between one to each other and assuming that p_L << p_H, then, the approximated values for f_L and f_H can be found as follows:

(9)

(10)

and relation (8) can be rewritten as:

(11)

For medium frequencies operation, i.e., f_L << frequency << f_H, the LNA gain is then:

(12)

which is in accordance with what is stated in literature [32].

The capacitances C₁ and C₂ are in the order of pF, therefore, the resistor R₂ must be in the order of TΩ, to ensure that the first pole f_L=1/(2πR₂C₂) of A_f(s), equation (8), has a value near or lower than 1.0 Hz.

High-value resistors, like R₂, can not be implemented in a conventional form in an integrated circuit due to the large area they would occupy.

Pseudo-resistors are a widely recognized method for implementing high-value resistors, as described in references [33]. Figure 2a also illustrates the implementation of resistors R₂ with pseudo-resistors. Each of these pseudo-resistors employs a series of two PMOS transistors, as detailed in the zoomed section of the figure. It has been found that these pseudo-resistors can reach values in the order of TΩ and occupy an area many orders of magnitude smaller than that of a conventional resistor implementation. These implementations are called "pseudo" because they mimic the behavior of a real resistor when small voltages are applied at their terminals. The red dots at terminal A of the pseudo-resistors R₂ serve to show how these pseudo-resistors connect to the LNA.

To achieve low noise and low power, even using an OpAmp with a simple configuration, the LNA design in this work was done through the use of metaheuristic algorithms, specifically particle swarm and simulated annealing [34,35]. To accomplish this task, a framework for transistor sizing and circuit optimization, based on metaheuristics, was applied. The framework requires for its operation a rating score for each design, obtained through electrical simulations. To acquire the design score, an aggregated objective function must be developed that generates a simulation file containing the circuit netlist, device sizes, and simulation commands. The function also triggers an electrical simulation, reads the results, and calculates the score. To carry out this calculation, the relevant circuit attributes are measured and predefined shaping functions. Figure 3, which reflect desired goals, are applied to the measured values. Finally, the fuction outputs are combined to build the score. Users can choose which shaping function to apply for each attribute result, enabling them to tailor the sizing and optimization to their specific needs. For example, if an attribute must be kept below a certain limit, the function < d1 d2( ) can be used; if the attribute should be minimized, the function / d1 d2( ) is applied.

Objective functions are tailored to specific classes of circuits, such as Voltage Reference Sources, OpAmps, Oscillators, Prescalesr, and neuronal LNAs. Once the objective function of a class is available, the framework will make possible the sizing/optimization of any circuit topology for which a SPICE like parameterized netlist, describing this particular topology, is provided. In Figure 4 is shown part of the parameterized SPICE netlist of the LNA (Figure 2 presents the circuit described in the netlist). For the netlist, X1, .., X12 are the circuit parameters that provide the device dimensions, and their values will be adjusted in the sizing/optimization process. The level of detail included in the netlist, such as the areas and perimeters of the transistor drain/source, parasitic elements, etc., as well as the knowledge embedded in it, such as the fact that dimensios of M5 and M7 shoud be related to avoid a systematic offset, directly affects the quality of the optimization.

M1 1 in 4 4 pch L='X1*1u' W='X5*1u' AD='X5*1u*Wpadrao/2' PD ='X5*1u Wpadrao'

+AS= 'X5*1u*Wpadrao/2' PS = 'X5*1u + Wpadrao'

M2 3 ip 4 4 pch L='X1*1u' W = 'X5*1u' AD='X5*1u*Wpadrao/2' PD='X5*1u + Wpadrao'

+AS = 'X5*1u*Wpadrao/2' PS = 'X5*1u + Wpadrao'

M3 1 1 vs vs nch L ='X2*1u' W='X6*1u' AD='X6*1u*Wpadrao/2' PD ='X6*1u + Wpadrao'

+M = 'nint(X12)'

M4 3 1 vs vs nch L='X2*1u' W= X6*1u' AD='X6*1u*Wpadrao/2' PD ='X6*1u + Wpadrao'

+M = 'nint(X12)'

M5 4 bias vd vd pch L='X3*1u' W='X7*1u' AD='X7*1u*Wpadrao/2' PD='X7*1u + Wpadrao'

+M = '2*nint(X12)*nint(X8)'

M6 out 3 vs vs nch L='X2*1u' W='X6*1u' AD ='X6*1u*Wpadrao/2' PD ='X6*1u

+Wpadrao'

M7 out bias vd vd pch L = 'X3*1u' W='X7*1u' AD='X7*1u*Wpadrao/2' PD='X7*1u + Wpadrao'

+M= 'nint(X8)'

*** compensation

M8n 3 vd 5 vs nch L ='X4*1u' W ='X9*1u' AD ='X9*1u*Wpadrao/2' PD = 'X9*1u + Wpadrao'

+As = 'X9*1u*Wpadrao/2' Ps ='X9*1u + Wpadrao'

M8p 3 vs 5 vd pch L = 'X4*1u' W = '2*X9*1u' AD = '2*X9*1u*Wpadrao' PD = '2*X9*1u

+Wpadrao' +AS = '2*X9*1u*Wpadrao' Ps = '2*X9*1u + Wpadrao'

Cc 5 out 'X10*1p'

** Bias

M9 bias bias vd vd pch L = 'X3*1u' W = 'X7*1u' AD = 'X7*1u*Wpadrao/2' PD = 'X7*1u

+Wpadrao'

* external bias current

Ibb bias 0 DC '(10^X11)*1u'

Figure 1 Parameterized SPICE netlist for AmOp of Figure 2. X1, .. X12 are the wanted parameters of the sizing/optmization process.

The framework has already been employed for design of Reference Voltage Sources [36], OpAmps, LNAs, VCOs, Prescalers [37], etc. The metaheuristics available in it are genetic algorithms (GA), simulated annealing (SA), particle swarm (PSO), quatum QPSO (QPSO) among others.

In Figure 5 the operation flux of the framework is detailed. The sizing/optimization process starts with the selection of a circuit class for which an objective function is available. Next, a topology of the specified class is chosen, along with some parameter values (power supply, operation frequency), the goals of the sizing/optimization (power consuption, noise, gain, etc.), the shaping functions applied to each goal, and the search space (minimum and maximum allowed values for circuit parameters to be sized). Finally, a metaheuristic, along with execution conditions (initial solutions, stop condition, etc.) is selected, and the sizing/optimizing process begins. The process will continue until the stop condition is met, and the duration of the process can vary from a few minutes to several hours, depending on factors such as the size and operation of the circuit, the performed simulations, and the stop condition employed. In this work, the number of evaluated circuits was used as the stop condition.

For the design of a circuit, one or more sizing/optimization processes were performed. When multiple processes are applied, they may or may not be independent. In the latter case, the results of the optimization are used as initial conditions for the next.

For the calculation of the design score in the neuronal LNA class, the following attributes are taken in consideration: the Differential gain, Common Mode gain, CMRR (Commum Mode Rejection Rate), PSRR (Power Supply Rajection Rate), common mode volatage range, slew rate, and phase margin of the AmpOp; the gain, power consuption, input noise, low and high cut off frequency, and area of the LNA. The evaluations of the area do not require simulations and are estimated based on the width and length of the transistors and of capacitors.

Table 1 presents the simulated characteristics of the final version of the sized/optmized LNA.

Note that during the design otimization, an input noise of 4.0 μVrms was initially specified. However, achieving this level of noise requires a significant amount of power consuption in the technology applied, due to various factors, including the large gate capacitance of the diferential pair transistors, M₁ and M₂. Technologies with larger minimum dimensions, like 180 nm technology, can be advantageously used in the design of low noise LNAs.

Several neural amplifiers aim for noise floors as low as 1-3 μVrms, which is significantly below the cortical recording noise [23,26]. For this reason, in our design, we increased the input noise while maintaining a low power consuption.

Table 2 lists the dimensions of the MOSFETs of the OpAmp and of the pseudo-resistors and the value of the capacitor C_c generated by the sizing/optimization algorithms. The listed Total (W/L) refers to the total value ratio and the other columns refere to the numer of paralel transistors and number of fingers applied. For example, the transistors M₁ and M₂ with Total (W/L)_1,2=(59 μm/0.52 μm) are composed of two parallel transistors, each with dimensions of (24.5 μm/0.52 μm) and, at the same time, containing ten fingers measuring (2.45 μm/0.52 μm). In another example, the transistor M₅ with Total (W/L)₅=(48 μm/2.22 μm) is composed by twenty four parallel transistors, each with dimensions of (2 μm/2.22 μm) containing only one finger for each of the twenty-four parallel transistors. The capacitor C_C was composed by 36 sub-capacitors of MIMcap type, which are connected in parallel and form a 6 × 6 array arrangement. Each sub-capacitor cell measures 10 μm × 10 μm.

2.2. Neurostimulator

The neurostimulators must preferably provide current pulses with biphasic shape due to electrical safety reasons, such as avoiding the accumulation of charges at the interfaces between the electrodes and the ionic species within the neuronal tissue [39]. Figure 6a,b illustrate two examples of pulse shaping, where the durations (or stimulation times), frequency, amplitudes, and interpulses delay of the pulses can be settled according medical requirements. The mean value of the signals is zero on both examples in Figure 6a,b, thanks for the arbitrary pulse shaping. The neurostimulator presented in this paper can generate other types of pulses with arbitrary shapes, gradients, amplitudes and mean values.

To maintain electrical safety, as previously mentioned, the neurostimulator circuit was designed to offer the capability of generating current with a biphasic waveform, which can invert the direction of charge injection in the neuronal tissue. The phenomenon to nullify charge accumulation is called charge balance [39]. Traditionally, the inversion of the current direction requires a bridge with H-topology [40], with the disadvantage of requiring four transistors for current inversion, increasing the number of necessary components and the programming complexity. However, the biggest disadvantage of the H-topology is that it requires access to two different contact points on the electrodes, which are normally unipolar. For these reasons, the circuit responsible for injecting the current into the electrodes is based on the Howland Current-Pump [41]. This circuit is easy to integrate because it uses low resistance values, that is, below 20 kΩ.

Figure 7a shows the schematic of the Current-Pump that implements the neurostimulator, which is a Howland Current-Pump circuit. The neurostimulator is composed by an OpAmp and four resistors {R₁, R₂, R₃, R₄}, all fully implemented using the mask layers of the TSMC 65 nm CMOS process.

Figure 7b presents the schematic of the OpAmp used by the Current-Pump. The PMOS M₈ also works as resistance Rc in series with the capacitor C_c. The series combination of Rc/C_c is placed in parallel with the capacitor C_x to form a struture that ensures unconditional stability of the OpAmp.

Table 3 lists the dimensions of the MOSFETs of the OpAmp and the internal capacitance Cx generated by the sizing/optimization algorithm. The relations (W/L) listed in the table follows the same logic of the relations in the Table 2. The same applies to the capacitors Cc and Cx.

3. Experimental Results

3.1. LNA

Figure 8a illustrates a photograph of the laboratory setup used during the experimental tests. Figure 9b illustrates how the common-mode voltage V_CM is produced. The circuit to produce the V_CM voltage uses a commercial Operational Amplifier TL081 with a symmetrical voltage supply of ±9 V, which is powered by two 9V batteries to ensure low noise at the output. The voltage supply of 1.2 V for the CMOS microdevice is obtained with the AMS1117 voltage regulator. In addition, each battery is connected in series with two potentiometers working as soft starters to prevent potential high gradients of charge currents of the MOSFET parasitic capacitances, particularly those used in the inputs of the LNA. The gate areas of the MOSFETs in the inputs of the LNA present high values, such as 59 μm × 0.52 μm, and, in consequence, a high gate capacitance.

Figure 8c shows the measured gain for several common-mode voltages V_CM and input signals with amplitude of 2 mV_pp. Figure 8d also shows the measured gain for several common-mode voltages V_CM and input signals with amplitude of 10 mV_pp. In both sets of plots, the simulation results are also shown (solid blue) to allow comparisons.

Table 4 lists the measured common-mode voltage V_CM,out at the output of LNA and its maximum gain G_max in terms of the input voltage V_in and the common-mode voltage V_CM.

The measurements, in general, agree well with the simulations. An increase in the common-mode voltage (V_CM), as depicted in Figure 8c, results in an improvement of the gain at low frequencies, but a corresponding degradation at high frequencies gains. On the other hand, the variations in V_CM within the range of [0.46, 0.54] V did not result in significantly different gains, thus demonstrating the robustness of this LNA with respect to V_CM, and amplifying the range of interest for acquiring neuronal signals with practically unchanged gain, resulting in a low potential for linear distortion of the signals during amplification.

The biasing voltage applied in the tests was V_BIAS = 0.68 mV, obtained using a bias resistence R_BIAS = 810 kΩ connected to the V_bias node, Figure 2b. This resulted in a biasing current I_BIAS = 770 nA, higher than the designed value. Even in such conditions, the LNA behavior is satisfactory, except by the total power consuption of 27.7 μW,

This LNA was also tested with a saline solution to emulate an ex-vivo situation and evaluate its performance in real in-vivo applications. Figure 9a illustrates a photograph of the experimental setup used in these measurements, while Figure 9b presents the measured gain for signals injected into the saline solution with an amplitude of 20 mV_pp. It should be noted that this was not the amplitude at the input of the amplifier, which was measured simultaneously with the amplitude at the output of LNA to calculate the LNA gain.

During the tests with saline solution, it was not possible to completely compensate for the effects of 60 Hz interference for input signals with frequencies less than 20 Hz. As a result, it was impossible to accurately characterize the LNA at these low frequencies. However, above 20 Hz, the gains, red points on the plot of measured gain, were easily and accurately measured. As seen in Figure 9b, the gain did not show any appreciable reduction in the frequency range between 20 Hz and 10 kHz. In fact, it is possible to observe that the gain remained high, with its maximum value of 40.1 dB at 30 Hz.

3.2. Neurostimualtor Circuit

The tests of this electronic module can be divided in static and dynamic tests. In static tests, the signals applied to the circuit do not change over time. On the other hand, in the dynamic tests, the different signals vary over time. The experimental setups used for both types of tests are essentially the same, except for the way in which the test signals were generated.

Figure 10a illustrates the schematic of the experimental setup for the static characterization of the neurostimulator circuit. This setup comprise a voltage follower, implemented with the operational amplifier TL084, to generate the common-mode voltage V_CM,electrode applied in the reference terminal of the electrode. The implantable electrode is represented by the load resistor R_LOAD.

Although it is possible to apply a resistor between the gate of M₉ node and V_dd, Figure 7b, to bias the OpAmp, it is more convenient to apply a voltage V_BIAS directly to this node, since an external voltage can be easily ajusted, making the testing process simpler. A circuit similar to the one used to generate V_CM,electrode was also used to generate and trim the bias voltage V_BIAS, which was settled to 315 mV.

The circuits used for generating the common mode voltages are similar to the one presented in Figure 8b, where the V_CM adjustment was done manually. The manual adjustament is not a real problem in our setup because only a few common-mode voltages were needed. Specifically, the common-mode voltage V_CM in the reference electrode was set between 0 V and 1.2 V in coarse steps of 0.3 V.

Two breakout boards based on the MCP4725 digital-to-analogue converter (DAC) with an I²C interface were used to provide fine tuning adjustments to the inputs V⁺ and V^- and, thus, precise adjustments of the currents injected into the load resistor R_LOAD. An Arduino board was selected to control the DACs.

Figure 10b shows a photograph of the experimental setup used in the static characterization of the Current-Pump. Figure 10c illustrates the currents for the various combinations of control and common mode voltages {V⁺, V^-, V_CM,electrode} in “raw” form to allow a clear and immediate visualization of the wide and quasi-symmetrical range of currents that are possible to generate with this Current-Pump. In contrast, Figure 10d illustrates the currents parameterized in terms of the reference voltage of the electrode V_CM,electrode and the inverting input voltage V^-. The output current was determined by the following expression:

(13)

where V_out is the output voltage of Current-Pump (node X in Figure 8a)

A load resistance of R_LOAD = 986.5 Ω was used for these tests. The output voltage V_out can range from 0 V to 1.2 V, therefore, the output current I_out can either be positive or negative, simply making the voltage of the reference electrode V_CM,electrode either equal to 0 V or 1.2 V, respectively. As it is possible to observe in Figure 12c,d, other intermediate currents are possible to be generated. The inversion of current direction is mandatory in Deep Brain Stimulation applications.

The Current-Pump was able to generate stimulation currents from -325 μA to +318 μA. The path marked with the dashed yellow lines in Figure 12d illustrates how continuous current signals can be generated from -325 μA to +318 μA.

Figure 12a illustrates the schematic of the experimental setup for the dynamic characterization. Figure 12b shows the photograph of the experimental setup.

The frequency of the signal at V^- is ten times higher than the frequency of the signal applied at V⁺. The amplitude of both signals varies between 0 V and 1.2 V. These settings result in a wave, product of the two input waves, with a sliced sine shape . In this setup, the reference voltage V_CM,electrode of the electrode was manually adjusted between 0 V and 1.2 V.

Figure 12c shows the experimental results of the dynamic characterization. A set of sine waves with common-mode voltage of 0.6 V and different amplitudes were applied in the non-inverting input V⁺ with V^- and V_CM,electrode settled to one of the voltages {0, 0.6, 1.2} V. The voltage ΔV⁺ in the plot is the difference between the maximum and the minimum values of the voltage V⁺. The voltage ΔV⁺ is equal to 2A⁺ for a non-inverting input V⁺ of V⁺ = 0.6+A⁺.cos(2πft). The amplitude ΔV⁺ was swept from 0.2 V to 1.2 V in steps of 0.2 V. The non-inverting input V⁺ voltage variation is rail-to-rail for A⁺ = 0.6 V. Figure 12d shows the results for seven combinations of {V^-, V_CM,electrode} in the set {0, 0.6, 1.2} V. Each combination defines the admissible range of the output current, whose plane domains are bounded above and below by two straight lines. The upper line occurs for V⁺ = 0.6+ΔV⁺, while the bottom line occurs for V⁺ = 0.6-ΔV⁺. It is possible to observe in Figure 12d the abillity to dynamically sweep the complete current limit, ranging from I_max = +375 μA to I_min = -218 μA, simply selecting the most suitable voltage combination of {V⁺, V^-, V_CM,electrode}.

It is also possible to observe in Figure 12c that a limited set of voltage combination of {V⁺, V^-, V_CM,electrode} must be avoided, under the penalty of not being able to generate very specific values of electric current. These voltage combinations are associated with the “no-man's land” regions marked with gray shading. The “no-man's land” regions are the combinations that are not contained in the set of the seven plane domains for the different voltage combinations {V⁺, V^-, V_CM,electrode}.

The measurements showed that these results are valid with all voltage combinations {V⁺, V^-, V_CM,electrode} for a frequency up to f_-3dB = 1.5 MHz. This frequency is the one that narrows the current range I_max-I_min to -3 dB. For example, the measurements showed that I_max = +297 μA and I_min = +248.4 μA for V⁺ = 0.6+0.1cos(2πft) or ΔV⁺ = 0.2 V with f<f_-3dB/10, and V^- = 0 V and V_CM,electrode = 0 V. This results on ΔI_out = I_max-I_min = +49 μA. The measurements also showed ΔI_out = (+49)×(2)^-1/2×(10^-6) = +34.6 μA for f = f_-3dB = 1.5 MHz.

4. Conclusions

This paper presented a low-noise amplifier (LNA) and a neurostimulator circuit, which were optimized for application on Closed-Loop Deep-Brain Stimulation (CLDBS). The LNA and neurostimulator were designed and fabricated in the CMOS 65 nm from TSMC. Table 5 compares this LNA with a few related key works found in the literature [12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32]. It was calculated the figure-of-merit (FOM) to better rank and compare this work with the others with respect to the internal noise-power consuption trade off. The noise efficiency factor (NEF) was introduced in 1987 by Steyaert et al. [38], and since then, it has been widely used. It is given by:

(14)

where I_total is the total current absorbed by the amplifier stage (this current excludes the amount absorbed by the bias stage), U_T is the thermal voltage given by kT/q (≈ 26 mV at the room temperature of 300 K), k is the Boltzmann constant, T is the room temperature expressed in Kelvin, IRN [V_rms] is the total input-referred noise, and BW is the LNA bandwidth.

It must be noted that this FOM compares the noise-power trade-off with that of a single ideal bipolar transistor. The lowest the FOM, the better will be the LNA with relation to the global noise performance.

Two important observations must be made regarding the results presented in Table 5: the two circuits with the lowest NEF, [24,28], use a single-input CMOS inverter as the first gain stage. The invert has half the number of transistors compared to the inpu stage of an OpAmp, and therefore introduces approximately half the amount of power noise. Consequently, the NEF is reduced by (2)^½ ; implementations with technologies with higher minimum length, [29,30,31,32], have a better NEF.

The LNA presented in this work exhibits an NEF that is comparable to the best ones found in the literature. This result is partly due to the sizing/optimization process performed through the application of metaheuristics.

Table 6 compares the features of this neurostimulator circuit with few related key works found in the literature [42,43,44,45,46,47,48]. All works listed in Table 6 were implemented using CMOS components. The neurostimulator presented in this paper and the neurostimulator presented by Adams et al [46] are the only ones that simultaneously allows the generation of current signals with non-standard waveforms and are suitable for delayed feedback.

To conclude, Figure 12 shows a photograph of the fabricated CMOS microdevice, which occupies 1.8 mm × 1.8 mm of area. Moreover, this figure also makes an emphasis to the LNA and neurostimulator presented in this paper.

Figure 12. Photograph of the fabricated CMOS microdevice (1.8 mm × 1.8 mm), with emphasis to the LNA presented in this paper and to one of the ESD protections.

Figure 12. Photograph of the fabricated CMOS microdevice (1.8 mm × 1.8 mm), with emphasis to the LNA presented in this paper and to one of the ESD protections.