Mai, X.-C.; Chen, S.-L.; Chen, H.-W.; Lee, Y.-M. Impacts of Floating Poly on Electrostatic Discharge Protection of Power-Managed High-Voltage Laterally Diffused Metal Oxide Semiconductor Components. Electronics2023, 12, 2803.
Mai, X.-C.; Chen, S.-L.; Chen, H.-W.; Lee, Y.-M. Impacts of Floating Poly on Electrostatic Discharge Protection of Power-Managed High-Voltage Laterally Diffused Metal Oxide Semiconductor Components. Electronics 2023, 12, 2803.
Mai, X.-C.; Chen, S.-L.; Chen, H.-W.; Lee, Y.-M. Impacts of Floating Poly on Electrostatic Discharge Protection of Power-Managed High-Voltage Laterally Diffused Metal Oxide Semiconductor Components. Electronics2023, 12, 2803.
Mai, X.-C.; Chen, S.-L.; Chen, H.-W.; Lee, Y.-M. Impacts of Floating Poly on Electrostatic Discharge Protection of Power-Managed High-Voltage Laterally Diffused Metal Oxide Semiconductor Components. Electronics 2023, 12, 2803.
Abstract
This study employed a TSMC 0.18-µm 50 V process to establish a high-voltage n-LDMOS structure. In the reference device, the number of floating-poly (poly-2) turns was 7, and the width and spacing of each turn was 1 µm. Although increasing the number of turns reduces the peak field, directly reducing or increasing the number of poly-2 turns is a common practice. The present experiment was realized in three steps, namely fixing the number of occupied area adjustment turns, adjusting the width of each turn, and adjusting the distance between turns.
The first step was fixing the number of occupied area adjustment turns. The number of turns was increased from 7 to 9, and the number of turns was reduced to 5 and 3 in the reference group. A reduction in the number of turns led to a greater decrease in the peak field and increase in the breakdown voltage despite the area remaining unchanged. A comparison of the use of three turns with that of seven turns revealed that the maximum electric field decreased by 42%, from 4.17e+3 to 2.46e+3 V/cm, and that the breakdown voltage (VBK) increased from 30.2 to 35.84 V. The second step was adjusting the width of each turn from 1 to 1.4, 1.2, 0.8, and 0.6 µm in the reference group. This increase in width reduced the maximum electric field and led to a greater increase in VBK. When the width was increased to 1.4 µm, the maximum electric field decreased by 29% from 1.95e+3 to 1.4e+3 V/cm, and the VBK increased by 183% from 30.2 to 85.6 V. The third step was adjusting the spacing of each turn from 1 to 1.4, 1.2, 0.8, and 0.6 µm in the reference group. The results revealed that a reduction in the spacing led to a greater reduction in the maximum electric field and an in-crease in the VBK. When the pitch was reduced to 0.6 µm, the maximum electric field decreased by 33%, from 1.95e+3 to 1.32e+3 V/cm, and the VBK increased by 345%, from 30.2 to 134.4 V.
Keywords
breakdown voltage; electric field; floating-poly; lattice temperature; n-LDMOS
Subject
Engineering, Electrical and Electronic Engineering
Copyright:
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
